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how to build defect-detection app from source and list the revision of the source? #2

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TonyHo722 opened this issue Feb 17, 2022 · 11 comments

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@TonyHo722
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TonyHo722 commented Feb 17, 2022

I had try to create app in below command and the firmware files are come from https://github.com/Xilinx/kv260-firmware/tree/release-2021.1/defect-detect.
The result is ok to run defect-detect.ipynb in Jupyter notebook in target system.

petalinux-create -t apps --template fpgamanager -n my-0215fw --enable --srcuri "kv260-defect-detect.bit kv260-defect-detect.dtsi kv260-defect-detect.xclbin shell.json"

Note: I used 4 files from https://github.com/Xilinx/kv260-firmware/tree/release-2021.1/defect-detect to create the app

But I have issue when I replace .bin & .xclbin files as my build kv260-defect-detect-my-build.bit and kv260-defect-detect-my-build.xclbin in below command.

petalinux-create -t apps --template fpgamanager -n my-0215fw2 --enable --srcuri "kv260-defect-detect-my-build.bit kv260-defect-detect.dtsi kv260-defect-detect-my-build.xclbin shell.json"

I named the app to my-0215fw2, it with issue when run defect-detect.ipynb in Jupyter notebook. the picture with noise as below picture.

defect-detect-issue

Note: the kv260-defect-detect-my-build.bit and kv260-defect-detect-my-build.xclbin is built from https://github.com/Xilinx/kv260-vitis.
and I had follow this link Xilinx/kria-vitis-platforms#11 to built the .bin & .xclbin file.

I am not sure does it correct to just replace the .bin & .xclbin file?
I found the dmesg with error as below in my-0215fw2

[  131.753634] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13
[  131.758029] xilinx-csi2rxss 80030000.mipi_csi2_rx_subsystem: missing xlnx,csi-pxl-format property
[  131.758046] xilinx-csi2rxss: probe of 80030000.mipi_csi2_rx_subsystem failed with error -22
[  131.759530] xilinx-frmbuf b0000000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[  131.759616] xilinx-frmbuf b0000000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[  131.759985] clk-wizard 80020000.clk_wiz: clk_in_name: misc_clk_1
[  131.761729] xlnx-mixer b0010000.v_mix: vtc bridge property not present
[  131.761839] [drm:xlnx_mix_probe] *ERROR* No xlnx,vformat value for layer 0 in dts
[  131.761849] xlnx-mixer b0010000.v_mix: Failed to probe mixer
[  131.761965] xlnx-mixer: probe of b0010000.v_mix failed with error -22
[  131.762944] xilinx-vtc 80010000.v_tc: device found, version 6.020
[  131.764310] xilinx-video axi:vcap_capture_pipeline_mipi_csi2_rx_subsyst_0: graph parsing failed
[  131.765182] xilinx-video: probe of axi:vcap_capture_pipeline_mipi_csi2_rx_subsyst_0 failed with error -22

or I should create my own .dtsi file?
I don't know how to create .dtsi file, any comment about how to create it?
I had follow "Generate .dtsi from .xsa using DTG" from https://xilinx.github.io/kria-apps-docs/creating_applications/1.0/build/html/docs/creating_applications_dtsi_dtbo_generation.html but it still fail.

I found in .dtsi file I generated from .xsa file as below.
should I update the firmware-name in the .dtsi file?

	fragment@0 {
		target = <&fpga_full>;
		overlay0: __overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			firmware-name = ".bin";
			resets = <&zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118>, <&zynqmp_reset 119>;
		};
	};

I also found in https://github.com/Xilinx/kv260-firmware/blob/release-2021.1/defect-detect/kv260-defect-detect.dtsi with zocl:
it is not found from my .dtsi file which generated from .xsa file.
should I add below in my .dtsi file?

	/* zocl */
	zocl: zyxclmm_drm {
		compatible = "xlnx,zocl";
		status = "okay";
		interrupt-parent = <&gic>;
		interrupts = <0 89  4>, <0 90  4>, <0 91  4>, <0 92  4>,
				<0 93  4>, <0 94  4>, <0 95  4>, <0 96  4>;
	};



Note: my KV260 target system without AR0144 mipi camera module, I used camera, I used playback=5 in defect-detect.ipynb in Jupyter notebook to test it.

# 0 for file input and file sink
# 1 for Live normal mode
# 2 for Live Demo mode
# 3 File In Display Out
# 4 Live In and File Out
# 5 File In Display Out Demo Mode
playback = 5
filesinkpath="/home/petalinux"
@jue-s
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jue-s commented Feb 21, 2022

hi Tony,
I am trying to understand what your goal is. Are you trying to change defect detect with a different accelerator? in your comment here:

But I have issue when I replace .bin & .xclbin files as my build kv260-defect-detect-my-build.bit and kv260-defect-detect-my-build.xclbin in below command.
petalinux-create -t apps --template fpgamanager -n my-0215fw2 --enable --srcuri "c kv260-defect-detect.dtsi kv260-defect-detect-my-build.xclbin shell.json"

I didnt see a .bit file. Also please note, xmutil expects a .bit.bin file, not a .bit file (please see step 3 here to convert: https://xilinx.github.io/kria-apps-docs/creating_applications/1.0/build/html/docs/creating_applications_vitis_accel_flow.html#step-3 )

There's also a different way to move files onto target:
https://xilinx.github.io/kria-apps-docs/creating_applications/1.0/build/html/docs/creating_applications_target.html

in my comment here i am referring to pages under https://xilinx.github.io/kria-apps-docs/creating_applications/1.0/build/html/index.html - it would be good to understand what your goal is so I can understand which flow you are sort of going through. Then I maybe able to help further.

@TonyHo722
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TonyHo722 commented Mar 3, 2022

@jue-s

  1. my goal is trying to build the defect detection app and petalinux boot image from the source code and study it. but I have issue in build the defect detection app.
  2. I had update my typo in top of this thread and also as below.
petalinux-create -t apps --template fpgamanager -n my-0215fw2 --enable --srcuri "kv260-defect-detect-my-build.bit kv260-defect-detect.dtsi kv260-defect-detect-my-build.xclbin shell.json"
  1. I will follow the link you provided and update the status in this thread. (https://xilinx.github.io/kria-apps-docs/creating_applications/1.0/build/html/docs/creating_applications_vitis_accel_flow.html#step-3 )

Thanks

@TonyHo722
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TonyHo722 commented Mar 4, 2022

@jue-s,

I think my title need to change to "how to build defect-detection app from source and list the revision of the source?"
I list the source I used as below, should I change it for build defect-detection app?

- petalinux : xilinx-k26-starterkit-v2021.1-final.bsp
- vivado: 2020.2.2
- kv260-vitis: branch = release-2020.2.2_k26
- device-tree: branch = release-2020.2.2_k26

I got error in dmesg. I list the sequence of how I do it in below

petalinux-create

(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ petalinux-create -t apps --template fpgamanager -n tony-0303fw-release-2020.2.2-k26 --enable --srcuri "/home/tonyho/Downloads/kv260-tony-firmware/kv260_ispMipiRx_vmixDP_wrapper.bit /home/tonyho/petalinux/2021.1/tools/xsct/release-2020.2.2_k26/pl.dtsi /home/tonyho/Downloads/kv260-tony-firmware/defect-detect.xclbin  /home/tonyho/Downloads/kv260-firmware/defect-detect/shell.json" --force
INFO: Create apps: tony-0303fw-release-2020.2.2-k26
WARNING: Component "/home/tonyho/petalinux/2021.1/tony_0215/project-spec/meta-user/recipes-apps/tony-0303fw-release-2020.2.2-k26" already exists.
WARNING: --force parameter specified, overwriting
INFO: Copying source urls into the project directory
INFO: Creating fpgamanager/fpgamanager_dtg template apps required FPGA Manager to be enabled in petalinux-config
INFO: New apps successfully created in /home/tonyho/petalinux/2021.1/tony_0215/project-spec/meta-user/recipes-apps/tony-0303fw-release-2020.2.2-k26
INFO: Enabling created component...
INFO: Sourcing build environment
INFO: Silentconfig rootfs
INFO: tony-0303fw-release-2020.2.2-k26 has been enabled 

app files generated after petalinux-create

(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ ll -R /home/tonyho/petalinux/2021.1/tony_0215/project-spec/meta-user/recipes-apps/tony-0303fw-release-2020.2.2-k26
/home/tonyho/petalinux/2021.1/tony_0215/project-spec/meta-user/recipes-apps/tony-0303fw-release-2020.2.2-k26:
total 20
drwxr-xr-x  3 tonyho tonyho 4096  三   4 11:36 ./
drwxr-xr-x 26 tonyho tonyho 4096  三   4 11:36 ../
drwxr-xr-x  2 tonyho tonyho 4096  三   4 11:36 files/
-rw-rw-r--  1 tonyho tonyho 1209  三   4 11:36 README
-rw-rw-r--  1 tonyho tonyho  523  三   4 11:36 tony-0303fw-release-2020.2.2-k26.bb

/home/tonyho/petalinux/2021.1/tony_0215/project-spec/meta-user/recipes-apps/tony-0303fw-release-2020.2.2-k26/files:
total 15328
drwxr-xr-x 2 tonyho tonyho    4096  三   4 11:36 ./
drwxr-xr-x 3 tonyho tonyho    4096  三   4 11:36 ../
-rw-rw-r-- 1 tonyho tonyho 7871161  二  11 17:29 defect-detect.xclbin
-rw-rw-r-- 1 tonyho tonyho 7797828  二  11 17:29 kv260_ispMipiRx_vmixDP_wrapper.bit
-rw-rw-r-- 1 tonyho tonyho   10400  二  16 14:47 pl.dtsi
-rw-rw-r-- 1 tonyho tonyho      57  一  10 19:30 shell.json
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ 

petalinux-build

(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ petalinux-build
[INFO] Sourcing buildtools
[INFO] Building project
[INFO] Sourcing build environment
[INFO] Generating workspace directory
INFO: bitbake petalinux-image-minimal
NOTE: Started PRServer with DBfile: /home/tonyho/petalinux/2021.1/tony_0215/build/cache/prserv.sqlite3, IP: 127.0.0.1, PORT: 36893, PID: 27654
Loading cache: 100% |#######################################################################################################################################################################| Time: 0:00:01
Loaded 5121 entries from dependency cache.
Parsing recipes: 100% |#####################################################################################################################################################################| Time: 0:00:01
Parsing of 3494 .bb files complete (3485 cached, 9 parsed). 5129 targets, 269 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |##################################################################################################################################################################| Time: 0:00:20
Sstate summary: Wanted 536 Found 519 Missed 17 Current 3807 (96% match, 99% complete)
NOTE: Executing Tasks
NOTE: Tasks Summary: Attempted 12030 tasks of which 11999 didn't need to be rerun and all succeeded.
INFO: Failed to copy built images to tftp dir: /tftpboot
[INFO] Successfully built project
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ 

app files generated after petalinux-build

(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ ll -R ~/petalinux/2021.1/tony_0215/build/tmp/sysroots-components/zynqmp_generic/tony-0303fw-release-2020.2.2-k26/lib/firmware/xilinx/tony-0303fw-release-2020.2.2-k26/
/home/tonyho/petalinux/2021.1/tony_0215/build/tmp/sysroots-components/zynqmp_generic/tony-0303fw-release-2020.2.2-k26/lib/firmware/xilinx/tony-0303fw-release-2020.2.2-k26/:
total 15344
drwxr-xr-x 2 tonyho tonyho    4096  三   4 11:38 ./
drwxr-xr-x 3 tonyho tonyho    4096  三   4 11:38 ../
-rw-r--r-- 1 tonyho tonyho      57  三   4 11:38 shell.json
-rw-r--r-- 1 tonyho tonyho 7807932  三   4 11:38 tony-0303fw-release-2020.2.2-k26.bit.bin
-rw-r--r-- 1 tonyho tonyho   13265  三   4 11:38 tony-0303fw-release-2020.2.2-k26.dtbo
-rw-r--r-- 1 tonyho tonyho 7871161  三   4 11:38 tony-0303fw-release-2020.2.2-k26.xclbin

use SFTP to put below files to target system

-rw-r--r-- 1 tonyho tonyho      57  三   4 11:38 shell.json
-rw-r--r-- 1 tonyho tonyho 7807932  三   4 11:38 tony-0303fw-release-2020.2.2-k26.bit.bin
-rw-r--r-- 1 tonyho tonyho   13265  三   4 11:38 tony-0303fw-release-2020.2.2-k26.dtbo
-rw-r--r-- 1 tonyho tonyho 7871161  三   4 11:38 tony-0303fw-release-2020.2.2-k26.xclbin

I put the file in below location in target system

xilinx-k26-starterkit-2021_1ubuntuVM-0215-add-3-app:/lib/firmware/xilinx/tony-0303fw-release-2020.2.2-k26$ ls -l
total 15336
-rw-r--r-- 1 root root      57 Mar  3 19:57 shell.json
-rw-r--r-- 1 root root 7807932 Mar  3 19:57 tony-0303fw-release-2020.2.2-k26.bit.bin
-rw-r--r-- 1 root root   13265 Mar  3 19:57 tony-0303fw-release-2020.2.2-k26.dtbo
-rw-r--r-- 1 root root 7871161 Mar  3 19:57 tony-0303fw-release-2020.2.2-k26.xclbin

sudo xmutil loapapp

xilinx-k26-starterkit-2021_1ubuntuVM-0215-add-3-app:~$ sudo xmutil unloadapp kv260-dp
Accelerator successfully removed.
xilinx-k26-starterkit-2021_1ubuntuVM-0215-add-3-app:~$ sudo xmutil loadapp tony-0303fw-release-2020.2.2-k26
Accelerator loaded to slot 0
xilinx-k26-starterkit-2021_1ubuntuVM-0215-add-3-app:~$ sudo xmutil listapps
                     Accelerator                            Base           Type    #slots         Active_slot

             kv260-defect-detect             kv260-defect-detect       XRT_FLAT         0                  -1
                tony-0215fw-tdsi                tony-0215fw-tdsi       XRT_FLAT         0                  -1
             tony-copy-from-good             tony-copy-from-good       XRT_FLAT         0                  -1
                     tony-0215fw                     tony-0215fw       XRT_FLAT         0                  -1
                  tony-0215f-bit                  tony-0215f-bit       XRT_FLAT         0                  -1
                tony-0215fw-dtsi                tony-0215fw-dtsi       XRT_FLAT         0                  -1
                tony-0215fw-copy                tony-0215fw-copy       XRT_FLAT         0                  -1
tony-0303fw-release-2020.2.2-k26tony-0303fw-release-2020.2.2-k26       XRT_FLAT         0                  0,
              tony-0215fw-xclbin              tony-0215fw-xclbin       XRT_FLAT         0                  -1
                    tony-0215fw2                    tony-0215fw2       XRT_FLAT         0                  -1
                        kv260-dp                        kv260-dp       XRT_FLAT         0                  -1

dmesg error after loadapp - tony-0303fw-release-2020.2.2-k26

[  101.994095] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name
[  101.994107] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/resets
[  101.994684] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay0
[  101.994700] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay1
[  101.994715] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0
[  101.994730] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0
[  101.994756] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking1
[  101.994772] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay2
[  101.994787] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_iic_0
[  101.994801] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0
[  101.994888] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_vip_0
[  101.994904] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_1
[  101.994963] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/capture_pipeline_mipi_csi2_rx_subsyst_0
[  101.994983] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/mipi_csi_portscapture_pipeline_mipi_csi2_rx_subsyst_0
[  101.995004] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/mipi_csi_port0capture_pipeline_mipi_csi2_rx_subsyst_0
[  101.995020] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/mipi_csirx_outcapture_pipeline_mipi_csi2_rx_subsyst_0
[  101.995035] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/mipi_csi_port1capture_pipeline_mipi_csi2_rx_subsyst_0
[  101.995050] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/mipi_csi_incapture_pipeline_mipi_csi2_rx_subsyst_0
[  101.995065] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_2
[  101.995080] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/capture_pipeline_v_frmbuf_wr_0
[  101.995095] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/display_pipeline_clk_wiz_0
[  101.995110] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/display_pipeline_v_mix_0
[  101.995127] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/crtc_mixer_portdisplay_pipeline_v_mix_0
[  101.995142] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/xx_mix_masterdisplay_pipeline_v_mix_0
[  101.995156] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/xx_mix_overlay_1display_pipeline_v_mix_0
[  101.995172] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/xx_mix_overlay_2display_pipeline_v_mix_0
[  101.995187] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/xx_mix_overlay_3display_pipeline_v_mix_0
[  101.995202] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/xx_mix_overlay_4display_pipeline_v_mix_0
[  101.995217] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/xx_mix_overlay_5display_pipeline_v_mix_0
[  101.995232] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/xx_mix_logodisplay_pipeline_v_mix_0
[  101.995248] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/display_pipeline_v_tc_0
[  101.995264] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/vcap_portscapture_pipeline_mipi_csi2_rx_subsyst_0
[  101.995280] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/vcap_portcapture_pipeline_mipi_csi2_rx_subsyst_0
[  101.995295] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/capture_pipeline_v_frmbuf_wr_0capture_pipeline_mipi_csi2_rx_subsyst_0
[  102.043059] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13
[  102.048845] xilinx-csi2rxss 80030000.mipi_csi2_rx_subsystem: invalid csi-pxl-format property!
[  102.048866] xilinx-csi2rxss: probe of 80030000.mipi_csi2_rx_subsystem failed with error -22
[  102.050667] xilinx-frmbuf b0000000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[  102.050767] xilinx-frmbuf b0000000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[  102.051307] clk-wizard 80020000.clk_wiz: clk_in_name: misc_clk_1
[  102.053009] xlnx-mixer b0010000.v_mix: vtc bridge property not present
[  102.053034] [drm:xlnx_mix_probe] *ERROR* No xlnx,vformat value for layer 0 in dts
[  102.053038] xlnx-mixer b0010000.v_mix: Failed to probe mixer
[  102.053057] xlnx-mixer: probe of b0010000.v_mix failed with error -22
[  102.053916] xilinx-vtc 80010000.v_tc: device found, version 6.020
[  102.054606] xilinx-video axi:vcap_capture_pipeline_mipi_csi2_rx_subsyst_0: graph parsing failed
[  102.054720] xilinx-video: probe of ax

@TonyHo722 TonyHo722 changed the title How to create .dtsi file for defect detection? how to build defect-detection app from source and list the revision of the source? Mar 4, 2022
@TonyHo722
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@jue-s

  • in dmesg log shows something wrong in device-tree.
[  102.048845] xilinx-csi2rxss 80030000.mipi_csi2_rx_subsystem: invalid csi-pxl-format property!

in https://github.com/Xilinx/kv260-firmware/blob/release-2021.1/defect-detect/kv260-defect-detect.dtsi

  • xlnx,csi-pxl-format = <0x1e>;
	isp_csiss: csiss@80030000 {
		compatible = "xlnx,mipi-csi2-rx-subsystem-5.0";
		reg = <0x0 0x80030000 0x0 0x10000>;
		clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk";
		clocks = <&misc_clk_0>, <&misc_clk_2>, <&misc_clk_1>;
		interrupt-parent = <&gic>;
		interrupts = <0 107 4>;
		xlnx,csi-pxl-format = <0x1e>;

but I found in /home/tonyho/petalinux/2021.1/tools/xsct/release-2020.2.2_k26/pl.dtsi => this file generated by DTG.

  • xlnx,csi-pxl-format = "YUV422_8bit"; => this setting cause the error
			capture_pipeline_mipi_csi2_rx_subsyst_0: mipi_csi2_rx_subsystem@80030000 {
				clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk";
				clocks = <&misc_clk_0>, <&misc_clk_2>, <&misc_clk_1>;
				compatible = "xlnx,mipi-csi2-rx-subsystem-5.1", "xlnx,mipi-csi2-rx-subsystem-5.0";
				interrupt-names = "csirxss_csi_irq";
				interrupt-parent = <&gic>;
				interrupts = <0 107 4>;
				reg = <0x0 0x80030000 0x0 0x10000>;
				xlnx,axis-tdata-width = <32>;
				xlnx,cal-mode = "NONE";
				xlnx,clk-io-swap = "false";
				xlnx,clk-lane-io-position = <0x0>;
				xlnx,clk-lp-io-swap = "false";
				xlnx,csi-en-activelanes = "false";
				xlnx,csi-en-crc = "true";
				xlnx,csi-filter-userdatatype = "false";
				xlnx,csi-opt1-regs = "false";
				xlnx,csi-pxl-format = "YUV422_8bit";

in the https://github.com/Xilinx/linux-xlnx/blob/master/drivers/media/platform/xilinx/xilinx-csi2rxss.c
the datatype need a cell(32 bit data) in dtsi file but the dtsi file generated by DTG provide a string = "YUV422_8bit"

	switch (xcsi2rxss->datatype) {
	case XCSI_DT_YUV4208B:
	case XCSI_DT_YUV4228B:
	case XCSI_DT_RGB444:
	case XCSI_DT_RGB555:
	case XCSI_DT_RGB565:
	case XCSI_DT_RGB666:
	case XCSI_DT_RGB888:
	case XCSI_DT_RAW6:
	case XCSI_DT_RAW7:
	case XCSI_DT_RAW8:
	case XCSI_DT_RAW10:
	case XCSI_DT_RAW12:
	case XCSI_DT_RAW14:
		break;
	case XCSI_DT_YUV42210B:
	case XCSI_DT_RAW16:
	case XCSI_DT_RAW20:
		if (!en_csi_v20) {
			ret = -EINVAL;
			dev_dbg(dev, "enable csi v2 for this pixel format");
		}
		break;
	default:
		ret = -EINVAL;
	}
	if (ret < 0) {
		dev_err(dev, "invalid csi-pxl-format property!\n");
		return ret;
	}

I also found this link https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/128024605/DTG+limitation+for+multimedia+IPs

  • the DTG with some limitation.

My question is - Can I use the DTG to generate the dtsi file from defect-detection PL design (.xsa file)? or I need to manual modify the dtsi file generated from DTG?

in /home/tonyho/petalinux/2021.1/tools/xsct/release-2020.2.2_k26/pl.dtsi
I found some comment in the pl.dtsi file and I don't know how to modify it? does any example to do it?

  • /* This is a place holder node for a custom IP, user may need to update the entries */
			axi_vip_0: axi_vip@a0000000 {
				/* This is a place holder node for a custom IP, user may need to update the entries */
				clock-names = "aclk";
				clocks = <&misc_clk_1>;
				compatible = "xlnx,axi-vip-1.1";
				reg = <0x0 0xa0000000 0x0 0x10000>;
				xlnx,axi-addr-width = <0x28>;
  • /* Fill cfa-pattern=rggb for raw data types, other fields video-format and video-width user needs to fill */
					mipi_csi_port0capture_pipeline_mipi_csi2_rx_subsyst_0: port@0 {
						/* Fill cfa-pattern=rggb for raw data types, other fields video-format and video-width user needs to fill */
						reg = <0>;
						xlnx,cfa-pattern = "rggb";
						xlnx,video-format = <12>;
						xlnx,video-width = <8>;
						mipi_csirx_outcapture_pipeline_mipi_csi2_rx_subsyst_0: endpoint {
							remote-endpoint = <&capture_pipeline_v_frmbuf_wr_0capture_pipeline_mipi_csi2_rx_subsyst_0>;
						};
					};
*/
  • /* Fill cfa-pattern=rggb for raw data types, other fields video-format,video-width user needs to fill */
  • /* User need to add something like remote-endpoint=<&out> under the node csiss_in:endpoint */
					mipi_csi_port1capture_pipeline_mipi_csi2_rx_subsyst_0: port@1 {
						/* Fill cfa-pattern=rggb for raw data types, other fields video-format,video-width user needs to fill */
						/* User need to add something like remote-endpoint=<&out> under the node csiss_in:endpoint */
						reg = <1>;
						xlnx,cfa-pattern = "rggb";
						xlnx,video-format = <12>;
						xlnx,video-width = <8>;
						mipi_csi_incapture_pipeline_mipi_csi2_rx_subsyst_0: endpoint {
						};
					};

@jue-s
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jue-s commented Mar 4, 2022

@TonyHo722 thanks for the detailed write up.

first - you will need to align tool version to the bsp version. you should be using 21.1 tools with 21.1 bsp, it will not work otherwise. you are currently using 2020.2

this command below, can you tell me what it should do?
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ petalinux-create -t apps --template fpgamanager -n tony-0303fw-release-2020.2.2-k26 --enable --srcuri "/home/tonyho/Downloads/kv260-tony-firmware/kv260_ispMipiRx_vmixDP_wrapper.bit /home/tonyho/petalinux/2021.1/tools/xsct/release-2020.2.2_k26/pl.dtsi /home/tonyho/Downloads/kv260-tony-firmware/defect-detect.xclbin /home/tonyho/Downloads/kv260-firmware/defect-detect/shell.json" --force
the command didnt seem to have used the released bsp at all, so i am not sure if what you are doing above would work. you can see in the tutorials that this is the way to generate a petalinux project:
petalinux-create -t project -s xilinx-k26-starterkit-v2021.1-final.bsp
please refer to: https://xilinx.github.io/kria-apps-docs/main/build/html/docs/build_petalinux.html and you maybe interested in "Enable Xilinx Application Packages" section to pull in code at build time to view

just want to make sure the basics is good before we go into more details into the other questions

@TonyHo722
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@jue-s,

1. base on your comment, I think I need provide my detail flow for you to check what I miss.

this command below, can you tell me what it should do?
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ petalinux-create -t apps --template fpgamanager -n tony-0303fw-release-2020.2.2-k26 --enable --srcuri "/home/tonyho/Downloads/kv260-tony-firmware/kv260_ispMipiRx_vmixDP_wrapper.bit /home/tonyho/petalinux/2021.1/tools/xsct/release-2020.2.2_k26/pl.dtsi /home/tonyho/Downloads/kv260-tony-firmware/defect-detect.xclbin /home/tonyho/Downloads/kv260-firmware/defect-detect/shell.json" --force

My flow to build petalinux image and app as below.

Step 1. create petalinux project and put in /home/tonyho/petalinux/2021.1/tony_0215

(base) tonyho@ubuntu3:~/petalinux/2021.1$ petalinux-create -t project -s ~/Downloads/xilinx-k26-starterkit-v2021.1-final.bsp -n tony_0215
INFO: Create project: tony_0215
INFO: New project successfully created in /home/tonyho/petalinux/2021.1/tony_0215

Step 2. add BOARD_VARIANT

(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ echo 'BOARD_VARIANT = "kv"' >>  project-spec/meta-user/conf/petalinuxbsp.conf
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ echo 'CONFIG_packagegroup-kv260-smartcam' >> project-spec/meta-user/conf/user-rootfsconfig
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ echo 'CONFIG_packagegroup-kv260-aibox-reid' >> project-spec/meta-user/conf/user-rootfsconfig
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ echo 'CONFIG_packagegroup-kv260-defect-detect' >> project-spec/meta-user/conf/user-rootfsconfig
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ echo 'CONFIG_packagegroup-kv260-nlp-smartvision' >> project-spec/meta-user/conf/user-rootfsconfig

Step 3. petalinux-config -c rootfs

  • select user packages ---> packagegroup-kv260-defect-detect
  • Then save and exit the configuration.
(base) tonyho@ubuntu3:~/petalinux/2021.1/xilinx-k26-starterkit-2021.1$ petalinux-config -c rootfs
[INFO] Sourcing buildtools
[INFO] Generating Kconfig for project
[INFO] Silentconfig project
[INFO] Generating kconfig for Rootfs
[INFO] Menuconfig rootfs


*** End of the configuration.
*** Execute 'make' to start the build or try 'make help'.

[INFO] Generating plnxtool conf
[INFO] Successfully configured rootfs

Step 4. build petalinux image

(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ petalinux-build

Step 5. Add New FPGA Firmware(app) for defect-detection.

  • this step is for build the app, use parameter "-t apps"
(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ petalinux-create -t apps --template fpgamanager -n tony-0303fw-release-2020.2.2-k26 --enable --srcuri "/home/tonyho/Downloads/kv260-tony-firmware/kv260_ispMipiRx_vmixDP_wrapper.bit /home/tonyho/petalinux/2021.1/tools/xsct/release-2020.2.2_k26/pl.dtsi /home/tonyho/Downloads/kv260-tony-firmware/defect-detect.xclbin /home/tonyho/Downloads/kv260-firmware/defect-detect/shell.json" --force

Step 6. build petalinux image again to generate New FPGA Firmware

(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ petalinux-build

Step 7. New FPGA Firmware(app) files generated after petalinux-build

(base) tonyho@ubuntu3:~/petalinux/2021.1/tony_0215$ ll -R ~/petalinux/2021.1/tony_0215/build/tmp/sysroots-components/zynqmp_generic/tony-0303fw-release-2020.2.2-k26/lib/firmware/xilinx/tony-0303fw-release-2020.2.2-k26/
/home/tonyho/petalinux/2021.1/tony_0215/build/tmp/sysroots-components/zynqmp_generic/tony-0303fw-release-2020.2.2-k26/lib/firmware/xilinx/tony-0303fw-release-2020.2.2-k26/:
total 15344
drwxr-xr-x 2 tonyho tonyho    4096  三   4 11:38 ./
drwxr-xr-x 3 tonyho tonyho    4096  三   4 11:38 ../
-rw-r--r-- 1 tonyho tonyho      57  三   4 11:38 shell.json
-rw-r--r-- 1 tonyho tonyho 7807932  三   4 11:38 tony-0303fw-release-2020.2.2-k26.bit.bin
-rw-r--r-- 1 tonyho tonyho   13265  三   4 11:38 tony-0303fw-release-2020.2.2-k26.dtbo
-rw-r--r-- 1 tonyho tonyho 7871161  三   4 11:38 tony-0303fw-release-2020.2.2-k26.xclbin

2. I am confusing in your comment.

first - you will need to align tool version to the bsp version. you should be using 21.1 tools with 21.1 bsp, it will not work otherwise. you are currently using 2020.2

/home/tonyho/Downloads/kv260-tony-firmware/kv260_ispMipiRx_vmixDP_wrapper.bit 
/home/tonyho/Downloads/kv260-tony-firmware/defect-detect.xclbin

@TonyHo722
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@jue-s

for align tool version, I had done as below but it is no help

- petalinux : xilinx-k26-starterkit-v2021.1-final.bsp
- vivado: 2021.1
- kv260-vitis: branch = release-2021.1
- device-tree: branch = release-2021.1

I check the pl. dtsi file still with below comment,

  • /* This is a place holder node for a custom IP, user may need to update the entries */
  • /* Fill cfa-pattern=rggb for raw data types, other fields video-format and video-width user needs to fill */
  • /* Fill cfa-pattern=rggb for raw data types, other fields video-format,video-width user needs to fill */
  • /* User need to add something like remote-endpoint=<&out> under the node csiss_in:endpoint */

I used below comment to generate .dtsi file

xsct
hsi open_hw_design /home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/kv260_ispMipiRx_vmixDP_save0307-2021.1.xsa
hsi set_repo_path /home/tonyho/workspace/device-tree-xlnx
hsi create_sw_design device-tree -os device_tree -proc psu_cortexa53_0
hsi set_property CONFIG.dt_overlay true [hsi::get_os]
hsi generate_target -dir save0307-2021.1_xlnx_rel_v2021.1
hsi close_hw_design [hsi::current_hw_design]
exit

pl.dtsi file in this folder.

(base) tonyho@ubuntu3:~/petalinux/2021.1/tools/xsct$ ls save0307-2021.1_xlnx_rel_v2021.1
device-tree.mss  include  pcw.dtsi  pl.dtsi  system.dts  system-top.dts  zynqmp-clk-ccf.dtsi  zynqmp.dtsi

pl.dtsi content as below

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version: XSCT 2021.1
 * Today is: Mon Mar  7 16:00:20 2022
 */


/dts-v1/;
/plugin/;
/ {
	fragment@0 {
		target = <&fpga_full>;
		overlay0: __overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			firmware-name = ".bin";
			resets = <&zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118>, <&zynqmp_reset 119>;
		};
	};
	fragment@1 {
		target = <&amba>;
		overlay1: __overlay__ {
			afi0: afi0 {
				compatible = "xlnx,afi-fpga";
				config-afi = < 0 0>, <1 0>, <2 0>, <3 0>, <4 1>, <5 1>, <6 0>, <7 0>, <8 0>, <9 0>, <10 2>, <11 2>, <12 2>, <13 2>, <14 0x0>, <15 0x000>;
			};
			clocking0: clocking0 {
				#clock-cells = <0>;
				assigned-clock-rates = <99999001>;
				assigned-clocks = <&zynqmp_clk 71>;
				clock-output-names = "fabric_clk";
				clocks = <&zynqmp_clk 71>;
				compatible = "xlnx,fclk";
			};
			clocking1: clocking1 {
				#clock-cells = <0>;
				assigned-clock-rates = <99999001>;
				assigned-clocks = <&zynqmp_clk 72>;
				clock-output-names = "fabric_clk";
				clocks = <&zynqmp_clk 72>;
				compatible = "xlnx,fclk";
			};
		};
	};
	fragment@2 {
		target = <&amba>;
		overlay2: __overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			axi_iic_0: i2c@80040000 {
				#address-cells = <1>;
				#size-cells = <0>;
				clock-names = "s_axi_aclk";
				clocks = <&misc_clk_0>;
				compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
				interrupt-names = "iic2intc_irpt";
				interrupt-parent = <&gic>;
				interrupts = <0 106 4>;
				reg = <0x0 0x80040000 0x0 0x10000>;
			};
			misc_clk_0: misc_clk_0 {
				#clock-cells = <0>;
				clock-frequency = <99999000>;
				compatible = "fixed-clock";
			};
			axi_vip_0: axi_vip@a0000000 {
				/* This is a place holder node for a custom IP, user may need to update the entries */
				clock-names = "aclk";
				clocks = <&misc_clk_1>;
				compatible = "xlnx,axi-vip-1.1";
				reg = <0x0 0xa0000000 0x0 0x10000>;
				xlnx,axi-addr-width = <0x28>;
				xlnx,axi-aruser-width = <0x10>;
				xlnx,axi-awuser-width = <0x10>;
				xlnx,axi-buser-width = <0x0>;
				xlnx,axi-has-aresetn = <0x1>;
				xlnx,axi-has-bresp = <0x1>;
				xlnx,axi-has-burst = <0x1>;
				xlnx,axi-has-cache = <0x1>;
				xlnx,axi-has-lock = <0x1>;
				xlnx,axi-has-prot = <0x1>;
				xlnx,axi-has-qos = <0x1>;
				xlnx,axi-has-region = <0x0>;
				xlnx,axi-has-rresp = <0x1>;
				xlnx,axi-has-wstrb = <0x1>;
				xlnx,axi-interface-mode = <0x2>;
				xlnx,axi-protocol = <0x0>;
				xlnx,axi-rdata-width = <0x20>;
				xlnx,axi-rid-width = <0x10>;
				xlnx,axi-ruser-width = <0x0>;
				xlnx,axi-supports-narrow = <0x1>;
				xlnx,axi-wdata-width = <0x20>;
				xlnx,axi-wid-width = <0x10>;
				xlnx,axi-wuser-width = <0x0>;
			};
			misc_clk_1: misc_clk_1 {
				#clock-cells = <0>;
				clock-frequency = <274997250>;
				compatible = "fixed-clock";
			};
			capture_pipeline_mipi_csi2_rx_subsyst_0: mipi_csi2_rx_subsystem@80030000 {
				clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk";
				clocks = <&misc_clk_0>, <&misc_clk_2>, <&misc_clk_1>;
				compatible = "xlnx,mipi-csi2-rx-subsystem-5.1", "xlnx,mipi-csi2-rx-subsystem-5.0";
				interrupt-names = "csirxss_csi_irq";
				interrupt-parent = <&gic>;
				interrupts = <0 107 4>;
				reg = <0x0 0x80030000 0x0 0x10000>;
				xlnx,axis-tdata-width = <32>;
				xlnx,max-lanes = <4>;
				xlnx,ppc = <2>;
				xlnx,vfb ;
				mipi_csi_portscapture_pipeline_mipi_csi2_rx_subsyst_0: ports {
					#address-cells = <1>;
					#size-cells = <0>;
					mipi_csi_port0capture_pipeline_mipi_csi2_rx_subsyst_0: port@1 {
						/* Fill cfa-pattern=rggb for raw data types, other fields video-format and video-width user needs to fill */
						reg = <1>;
						xlnx,cfa-pattern = "rggb";
						xlnx,video-format = <12>;
						xlnx,video-width = <8>;
						mipi_csirx_outcapture_pipeline_mipi_csi2_rx_subsyst_0: endpoint {
							remote-endpoint = <&capture_pipeline_v_frmbuf_wr_0capture_pipeline_mipi_csi2_rx_subsyst_0>;
						};
					};
					mipi_csi_port1capture_pipeline_mipi_csi2_rx_subsyst_0: port@0 {
						/* Fill cfa-pattern=rggb for raw data types, other fields video-format,video-width user needs to fill */
						/* User need to add something like remote-endpoint=<&out> under the node csiss_in:endpoint */
						reg = <0>;
						xlnx,cfa-pattern = "rggb";
						xlnx,video-format = <12>;
						xlnx,video-width = <8>;
						mipi_csi_incapture_pipeline_mipi_csi2_rx_subsyst_0: endpoint {
							data-lanes = <1 2 3 4>;
						};
					};
				};
			};
			misc_clk_2: misc_clk_2 {
				#clock-cells = <0>;
				clock-frequency = <199998000>;
				compatible = "fixed-clock";
			};
			capture_pipeline_v_frmbuf_wr_0: v_frmbuf_wr@b0000000 {
				#dma-cells = <1>;
				clock-names = "ap_clk";
				clocks = <&misc_clk_1>;
				compatible = "xlnx,v-frmbuf-wr-2.2", "xlnx,axi-frmbuf-wr-v2.1";
				interrupt-names = "interrupt";
				interrupt-parent = <&gic>;
				interrupts = <0 108 4>;
				reg = <0x0 0xb0000000 0x0 0x10000>;
				reset-gpios = <&gpio 79 1>;
				xlnx,dma-addr-width = <32>;
				xlnx,dma-align = <16>;
				xlnx,max-height = <800>;
				xlnx,max-width = <1280>;
				xlnx,pixels-per-clock = <2>;
				xlnx,s-axi-ctrl-addr-width = <0x7>;
				xlnx,s-axi-ctrl-data-width = <0x20>;
				xlnx,vid-formats = "y8";
				xlnx,video-width = <8>;
			};
			display_pipeline_clk_wiz_0: clk_wiz@80020000 {
				#clock-cells = <1>;
				clock-names = "s_axi_aclk", "clk_in1";
				clock-output-names = "0x80020000-clk_out1";
				clocks = <&misc_clk_0>, <&misc_clk_1>;
				compatible = "xlnx,clk-wiz-6.0", "xlnx,clocking-wizard";
				reg = <0x0 0x80020000 0x0 0x10000>;
				speed-grade = <2>;
			};
			display_pipeline_v_mix_0: v_mix@b0010000 {
				clock-names = "ap_clk";
				clocks = <&misc_clk_1>;
				compatible = "xlnx,v-mix-5.1", "xlnx,mixer-3.0", "xlnx,mixer-4.0", "xlnx,mixer-5.0";
				interrupt-names = "interrupt";
				interrupt-parent = <&gic>;
				interrupts = <0 104 4>;
				reg = <0x0 0xb0010000 0x0 0x10000>;
				reset-gpios = <&gpio 78 1>;
				xlnx,bpc = <8>;
				xlnx,dma-addr-width = <32>;
				xlnx,num-layers = <6>;
				xlnx,ppc = <1>;
				crtc_mixer_portdisplay_pipeline_v_mix_0: port@0 {
					reg = <0>;
				};
				xx_mix_masterdisplay_pipeline_v_mix_0: layer_0 {
					xlnx,layer-id = <0>;
					xlnx,layer-max-height = <2160>;
					xlnx,layer-max-width = <3840>;
					xlnx,layer-primary ;
				};
				xx_mix_overlay_1display_pipeline_v_mix_0: layer_1 {
					xlnx,layer-id = <1>;
					xlnx,layer-max-width = <1920>;
					xlnx,vformat = "GREY";
				};
				xx_mix_overlay_2display_pipeline_v_mix_0: layer_2 {
					xlnx,layer-id = <2>;
					xlnx,layer-max-width = <1920>;
					xlnx,vformat = "GREY";
				};
				xx_mix_overlay_3display_pipeline_v_mix_0: layer_3 {
					xlnx,layer-id = <3>;
					xlnx,layer-max-width = <1920>;
					xlnx,vformat = "GREY";
				};
				xx_mix_overlay_4display_pipeline_v_mix_0: layer_4 {
					xlnx,layer-id = <4>;
					xlnx,layer-max-width = <1920>;
					xlnx,vformat = "GREY";
				};
				xx_mix_overlay_5display_pipeline_v_mix_0: layer_5 {
					xlnx,layer-alpha ;
					xlnx,layer-id = <5>;
					xlnx,layer-max-width = <1920>;
					xlnx,vformat = "AR24";
				};
				xx_mix_logodisplay_pipeline_v_mix_0: logo {
					xlnx,layer-id = <6>;
					xlnx,logo-height = <64>;
					xlnx,logo-width = <64>;
				};
			};
			display_pipeline_v_tc_0: v_tc@80010000 {
				clock-names = "clk", "s_axi_aclk";
				clocks = <&display_pipeline_clk_wiz_0 0>, <&misc_clk_0>;
				compatible = "xlnx,v-tc-6.2", "xlnx,v-tc-6.1";
				interrupt-names = "irq";
				interrupt-parent = <&gic>;
				interrupts = <0 105 4>;
				reg = <0x0 0x80010000 0x0 0x10000>;
				xlnx,generator ;
			};
			vcap_capture_pipeline_mipi_csi2_rx_subsyst_0 {
				compatible = "xlnx,video";
				dma-names = "port0";
				dmas = <&capture_pipeline_v_frmbuf_wr_0 0>;
				vcap_portscapture_pipeline_mipi_csi2_rx_subsyst_0: ports {
					#address-cells = <1>;
					#size-cells = <0>;
					vcap_portcapture_pipeline_mipi_csi2_rx_subsyst_0: port@0 {
						direction = "input";
						reg = <0>;
						capture_pipeline_v_frmbuf_wr_0capture_pipeline_mipi_csi2_rx_subsyst_0: endpoint {
							remote-endpoint = <&mipi_csirx_outcapture_pipeline_mipi_csi2_rx_subsyst_0>;
						};
					};
				};
			};
		};
	};
};

demsg error

[   41.400573] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13
[   41.405160] xilinx-csi2rxss 80030000.mipi_csi2_rx_subsystem: missing xlnx,csi-pxl-format property
[   41.405175] xilinx-csi2rxss: probe of 80030000.mipi_csi2_rx_subsystem failed with error -22
[   41.406432] xilinx-frmbuf b0000000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[   41.406521] xilinx-frmbuf b0000000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[   41.406893] clk-wizard 80020000.clk_wiz: clk_in_name: misc_clk_1
[   41.408695] xlnx-mixer b0010000.v_mix: vtc bridge property not present
[   41.408719] [drm:xlnx_mix_probe] *ERROR* No xlnx,vformat value for layer 0 in dts
[   41.408724] xlnx-mixer b0010000.v_mix: Failed to probe mixer
[   41.408756] xlnx-mixer: probe of b0010000.v_mix failed with error -22
[   41.409566] xilinx-vtc 80010000.v_tc: device found, version 6.020
[   41.410118] xilinx-video axi:vcap_capture_pipeline_mipi_csi2_rx_subsyst_0: graph parsing failed
[   41.410215] xilinx-video: probe of axi:vcap_capture_pipeline_mipi_csi2_rx_subsyst_0 failed with error -22

I think this issue is how to generate .dtsi file for the app.
does it any way can auto-generate it? or it need user manual modified?

@jue-s
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jue-s commented Mar 7, 2022

hi @TonyHo722
thank you for updating the tools and further trying out the applications. There is a gap in the documentation that i realized because of your question - so thank you. it iwll be fixed in future versions. we do need to manually update .dtsi file after it is generated. (you will notice that the .dtsi file also note that some places requires manual tuning). you can reference the .dtsi file here for defect detect:
https://github.com/Xilinx/kv260-firmware/blob/release-2021.1/defect-detect/kv260-defect-detect.dtsi

please note there's also this way of placing firmware on target to run (instead of doing it through petalinux):
https://xilinx.github.io/kria-apps-docs/creating_applications/1.0/build/html/docs/creating_applications_target.html

@TonyHo722
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@jue-s

I got it. I will try to manual tuning it.
Thanks

@TonyHo722
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@jue-s

Could you comment what revision of kv260-vitis can generate exact the same binary of below files in kv260-firmware?

https://github.com/Xilinx/kv260-firmware/blob/release-2021.1/defect-detect/kv260-defect-detect.xclbin
https://github.com/Xilinx/kv260-firmware/blob/release-2021.1/defect-detect/kv260-defect-detect.bit

does it as below?

- vivado: 2021.1
- kv260-vitis: branch = release-2021.1

If you can provide it then I can just use the .dtsi in below without modify and study the source.

https://github.com/Xilinx/kv260-firmware/blob/release-2021.1/defect-detect/kv260-defect-detect.dtsi

Thanks

@TonyHo722
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@jue-s

I can run the defect-detection from the binary I built from sourece now.

I used below revision to generate .xclbin and .bit file

- vivado: 2021.1
- kv260-vitis: branch = release-2021.1

the .xclbin and .bit file is generated from vivado 2021.1 and https://github.com/Xilinx/kv260-vitis branch = release_2021.1

/home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/defect-detect_save0307-2021.1.xclbin
/home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/kv260_ispMipiRx_vmixDP_wrapper_save0307-2021.1.bit

command as below to generate the app file

petalinux-create -t apps --template fpgamanager -n tony-0309fw-rel-v2021.1 --enable --srcuri "/home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/kv260_ispMipiRx_vmixDP_wrapper_save0307-2021.1.bit /home/tonyho/Downloads/kv260-firmware/defect-detect/kv260-defect-detect.dtsi /home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/defect-detect_save0307-2021.1.xclbin /home/tonyho/Downloads/kv260-firmware/defect-detect/shell.json" --force

Note: the .dtsi file is come from https://github.com/Xilinx/kv260-firmware/blob/release-2021.1/defect-detect/kv260-defect-detect.dtsi

the dmesg error after "sudo xmutil loadapp tony-0309fw-rel-v2021.1"

this may not a issue in the run defect-detect app

[  586.014607] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13

run python code in jupyter notebook and result is ok

image

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