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clk: zynqmp: Sync with mainline
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While upstreaming some changes have been made based on reviews.
This patch is syncing up them by reverting internal patches:
commit 3100e26 ("clk: zynqmp: Map ZYNQMP_CLK_SET_RATE_GATE with CCF"),
commit dee65b6 ("clk: zynqmp: Use firmware specific mux clock flags"),
commit a3cfc9e ("clk: zynqmp: Use firmware specific divider clock
flags"), commit 54ed8a7 ("clk: zynqmp: Use firmware specific common
clock flags"), commit 0851d74 ("clk: zynqmp: Handle divider specific
read only flag")

by upstream versions:
commit 03aea91 ("clk: zynqmp: Handle divider specific read only
flag"), commit 54530ed ("clk: zynqmp: Use firmware specific mux clock
flags"), commit 1b09c30 ("clk: zynqmp: Use firmware specific divider
clock flags"), commit 610a5d8 ("clk: zynqmp: Use firmware specific
common clock flags").

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
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@rajanv-xilinx
rajanv-xilinx authored and Michal Simek committed Aug 23, 2021
1 parent 89a2e4e commit 45cd007
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Showing 6 changed files with 86 additions and 65 deletions.
4 changes: 3 additions & 1 deletion drivers/clk/zynqmp/clk-gate-zynqmp.c
View file
Expand Up @@ -121,7 +121,9 @@ struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,

init.name = name;
init.ops = &zynqmp_clk_gate_ops;
init.flags = nodes->flag;

init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);

init.parent_names = parents;
init.num_parents = 1;

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39 changes: 25 additions & 14 deletions drivers/clk/zynqmp/clk-mux-zynqmp.c
View file
Expand Up @@ -96,6 +96,27 @@ static const struct clk_ops zynqmp_clk_mux_ro_ops = {
.get_parent = zynqmp_clk_mux_get_parent,
};

static inline unsigned long zynqmp_clk_map_mux_ccf_flags(
const u32 zynqmp_type_flag)
{
unsigned long ccf_flag = 0;

if (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_ONE)
ccf_flag |= CLK_MUX_INDEX_ONE;
if (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_BIT)
ccf_flag |= CLK_MUX_INDEX_BIT;
if (zynqmp_type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK)
ccf_flag |= CLK_MUX_HIWORD_MASK;
if (zynqmp_type_flag & ZYNQMP_CLK_MUX_READ_ONLY)
ccf_flag |= CLK_MUX_READ_ONLY;
if (zynqmp_type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST)
ccf_flag |= CLK_MUX_ROUND_CLOSEST;
if (zynqmp_type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN)
ccf_flag |= CLK_MUX_BIG_ENDIAN;

return ccf_flag;
}

/**
* zynqmp_clk_register_mux() - Register a mux table with the clock
* framework
Expand Down Expand Up @@ -126,22 +147,12 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
init.ops = &zynqmp_clk_mux_ro_ops;
else
init.ops = &zynqmp_clk_mux_ops;
init.flags = nodes->flag;

init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);

init.parent_names = parents;
init.num_parents = num_parents;
mux->flags = 0;
mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) ?
CLK_MUX_INDEX_ONE : 0;
mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) ?
CLK_MUX_INDEX_BIT : 0;
mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) ?
CLK_MUX_HIWORD_MASK : 0;
mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_READ_ONLY) ?
CLK_MUX_READ_ONLY : 0;
mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) ?
CLK_MUX_ROUND_CLOSEST : 0;
mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) ?
CLK_MUX_BIG_ENDIAN : 0;
mux->flags = zynqmp_clk_map_mux_ccf_flags(nodes->type_flag);
mux->hw.init = &init;
mux->clk_id = clk_id;

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10 changes: 2 additions & 8 deletions drivers/clk/zynqmp/clk-zynqmp.h
View file
Expand Up @@ -19,16 +19,8 @@
#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2)
/* do not gate even if unused */
#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3)
/* do not use the cached clk rate */
#define ZYNQMP_CLK_GET_RATE_NOCACHE BIT(6)
/* don't re-parent on rate change */
#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7)
/* do not use the cached clk accuracy */
#define ZYNQMP_CLK_GET_ACCURACY_NOCACHE BIT(8)
/* recalc rates after notifications */
#define ZYNQMP_CLK_RECALC_NEW_RATES BIT(9)
/* clock needs to run to set rate */
#define ZYNQMP_CLK_SET_RATE_UNGATE BIT(10)
/* do not gate, ever */
#define ZYNQMP_CLK_IS_CRITICAL BIT(11)

Expand Down Expand Up @@ -73,6 +65,8 @@ struct clock_topology {
u8 custom_type_flag;
};

unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag);

struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
const char * const *parents,
u8 num_parents,
Expand Down
50 changes: 26 additions & 24 deletions drivers/clk/zynqmp/clkc.c
View file
Expand Up @@ -271,6 +271,26 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
return ret;
}

unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag)
{
unsigned long ccf_flag = 0;

if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
ccf_flag |= CLK_SET_RATE_GATE;
if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE)
ccf_flag |= CLK_SET_PARENT_GATE;
if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT)
ccf_flag |= CLK_SET_RATE_PARENT;
if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED)
ccf_flag |= CLK_IGNORE_UNUSED;
if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT)
ccf_flag |= CLK_SET_RATE_NO_REPARENT;
if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL)
ccf_flag |= CLK_IS_CRITICAL;

return ccf_flag;
}

/**
* zynqmp_clk_register_fixed_factor() - Register fixed factor with the
* clock framework
Expand All @@ -292,6 +312,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
struct zynqmp_pm_query_data qdata = {0};
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
unsigned long flag;

qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
qdata.arg1 = clk_id;
Expand All @@ -303,9 +324,11 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
mult = ret_payload[1];
div = ret_payload[2];

flag = zynqmp_clk_map_common_ccf_flags(nodes->flag);

hw = clk_hw_register_fixed_factor(NULL, name,
parents[0],
nodes->flag, mult,
flag, mult,
div);

return hw;
Expand Down Expand Up @@ -385,35 +408,14 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology,
{
int i;
u32 type;
u32 flag;

for (i = 0; i < ARRAY_SIZE(response->topology); i++) {
type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);
if (type == TYPE_INVALID)
return END_OF_TOPOLOGY_NODE;
topology[*nnodes].type = type;
flag = FIELD_GET(CLK_TOPOLOGY_FLAGS, response->topology[i]);
topology[*nnodes].flag = 0;
topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_GATE) ?
CLK_SET_RATE_GATE : 0;
topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_PARENT) ?
CLK_SET_RATE_PARENT : 0;
topology[*nnodes].flag |= (flag & ZYNQMP_CLK_IGNORE_UNUSED) ?
CLK_IGNORE_UNUSED : 0;
topology[*nnodes].flag |= (flag & ZYNQMP_CLK_GET_RATE_NOCACHE) ?
CLK_GET_RATE_NOCACHE : 0;
topology[*nnodes].flag |= (flag &
ZYNQMP_CLK_SET_RATE_NO_REPARENT) ?
CLK_SET_RATE_NO_REPARENT : 0;
topology[*nnodes].flag |= (flag &
ZYNQMP_CLK_GET_ACCURACY_NOCACHE) ?
CLK_GET_ACCURACY_NOCACHE : 0;
topology[*nnodes].flag |= (flag & ZYNQMP_CLK_RECALC_NEW_RATES) ?
CLK_RECALC_NEW_RATES : 0;
topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_UNGATE) ?
CLK_SET_RATE_UNGATE : 0;
topology[*nnodes].flag |= (flag & ZYNQMP_CLK_IS_CRITICAL) ?
CLK_IS_CRITICAL : 0;
topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
response->topology[i]);
topology[*nnodes].type_flag =
FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
response->topology[i]);
Expand Down
44 changes: 27 additions & 17 deletions drivers/clk/zynqmp/divider.c
View file
Expand Up @@ -292,6 +292,29 @@ static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
return ret_payload[1];
}

static inline unsigned long zynqmp_clk_map_divider_ccf_flags(
const u32 zynqmp_type_flag)
{
unsigned long ccf_flag = 0;

if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED)
ccf_flag |= CLK_DIVIDER_ONE_BASED;
if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO)
ccf_flag |= CLK_DIVIDER_POWER_OF_TWO;
if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO)
ccf_flag |= CLK_DIVIDER_ALLOW_ZERO;
if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO)
ccf_flag |= CLK_DIVIDER_HIWORD_MASK;
if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST)
ccf_flag |= CLK_DIVIDER_ROUND_CLOSEST;
if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY)
ccf_flag |= CLK_DIVIDER_READ_ONLY;
if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO)
ccf_flag |= CLK_DIVIDER_MAX_AT_ZERO;

return ccf_flag;
}

/**
* zynqmp_clk_register_divider() - Register a divider clock
* @name: Name of this clock
Expand Down Expand Up @@ -323,29 +346,16 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
init.ops = &zynqmp_clk_divider_ro_ops;
else
init.ops = &zynqmp_clk_divider_ops;
/* CLK_FRAC is not defined in the common clk framework */
init.flags = nodes->flag & ~CLK_FRAC;

init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);

init.parent_names = parents;
init.num_parents = 1;

/* struct clk_divider assignments */
div->is_frac = !!((nodes->flag & CLK_FRAC) |
(nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
div->flags = 0;
div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ?
CLK_DIVIDER_ONE_BASED : 0;
div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
CLK_DIVIDER_POWER_OF_TWO : 0;
div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ?
CLK_DIVIDER_ALLOW_ZERO : 0;
div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
CLK_DIVIDER_HIWORD_MASK : 0;
div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ?
CLK_DIVIDER_ROUND_CLOSEST : 0;
div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ?
CLK_DIVIDER_READ_ONLY : 0;
div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ?
CLK_DIVIDER_MAX_AT_ZERO : 0;
div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag);
div->hw.init = &init;
div->clk_id = clk_id;
div->div_type = nodes->type;
Expand Down
4 changes: 3 additions & 1 deletion drivers/clk/zynqmp/pll.c
View file
Expand Up @@ -322,7 +322,9 @@ struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,

init.name = name;
init.ops = &zynqmp_pll_ops;
init.flags = nodes->flag;

init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);

init.parent_names = parents;
init.num_parents = 1;

Expand Down

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