arm64: zynqmp: Fix kr260 clock wiring

kr260 revA/revA01 is using discrete oscilator for DP (27MHz) and si5332 for
other clocks but clocks are different compare to kv260 that's why fix it to
aligned with the latest schematics.

On the other handle kr260 revB/revA03 also contains 74.25 MHz discrete
clock chip for SLVC-EC output which is not defined.

Link: https://lore.kernel.org/r/e87ae94979c6efc909740bb1a569505042e4f876.1706626255.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
State: pending

arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso

@@ -25,16 +25,22 @@
 		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
 	};
 
+	clk_27: clock0 { /* u86 - DP */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+
 	clk_125: si5332-0 { /* u17 - GEM0/1 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <125000000>;
 	};
 
-	clk_27: si5332-1 { /* u17 - DP */
+	clk_74: si5332-5 { /* u17 - SLVC-EC */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency = <27000000>;
+		clock-frequency = <74250000>;
 	};
 
 	clk_26: si5332-2 { /* u17 - USB */
@@ -49,13 +55,13 @@
 		clock-frequency = <156250000>;
 	};
 
-	clk_25_0: si5332-4 { /* u17 - GEM2 */
+	clk_25_0: si5332-1 { /* u17 - GEM2 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <25000000>;
 	};
 
-	clk_25_1: si5332-5 { /* u17 - GEM3 */
+	clk_25_1: si5332-4 { /* u17 - GEM3 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <25000000>;

arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso

@@ -60,6 +60,12 @@
 		#clock-cells = <0>;
 		clock-frequency = <25000000>;
 	};
+
+	clk_74: clock6 { /* u88 - SLVC-EC */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <74250000>;
+	};
 };
 
 &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */