arm64: versal: Add DT description for CPM5 Root port for Versal Premium

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit
  to enable and handle legacy interrupts.

Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>

arch/arm64/boot/dts/xilinx/versal.dtsi

@@ -635,6 +635,36 @@
 			};
 		};
 
+		cpm5_pcie: pcie@fcdd0000 {
+			device_type = "pci";
+			#address-cells = <3>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			compatible = "xlnx,versal-cpm5-host";
+			status = "disabled";
+			interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
+					<0 0 0 2 &pcie_intc_1 1>,
+					<0 0 0 3 &pcie_intc_1 2>,
+					<0 0 0 4 &pcie_intc_1 3>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-names = "misc";
+			interrupts = <0 72 4>;
+			interrupt-parent = <&gic>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
+				 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
+			msi-map = <0x0 &gic_its 0x0 0x10000>;
+			reg = <0x00 0xfcdd0000 0x00 0x1000>,
+			      <0x06 0x00000000 0x00 0x1000000>,
+			      <0x00 0xfce20000 0x00 0x1000000>;
+			reg-names = "cpm_slcr", "cfg", "cpm_csr";
+			pcie_intc_1: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
 		watchdog: watchdog@fd4d0000 {
 			compatible = "xlnx,versal-wwdt";
 			status = "disabled";