Xyce/ADMS: Real to integer conversion inconsistent with Accellera standard

[ngwood]

Xyce/ADMS uses C++ implicit conversion from double to int which performs truncation of the fraction part of the value. This is inconsistent with the Verilog-AMS Language Reference Manual (VAMS-LRM-2.4: 4.2.1.1 Real to integer conversion) which states the following. "Real numbers are converted to integers by rounding the real number to the nearest integer, rather than by truncating it. Implicit conversion takes place when a real number is assigned to an integer. If the fractional part of the real number is exactly 0.5, it shall be rounded away from zero."

Verilog-A (var should be assigned 2):

integer var;

var = 1.5;

C++ (var wrongly assigned 1):

int var=0.0;
//End of Block-local variables
var = 1.5;

[tvrusso]

All the open source ADMS back-ends rely on C or C++ implicit conversion. It may be inconsistent with the LRM, but it is not likely to be something that we address in short order.