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rsx_methods.cpp
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rsx_methods.cpp
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#include "stdafx.h"
#include "rsx_methods.h"
#include "RSXThread.h"
#include "Emu/Memory/vm.h"
#include "Emu/System.h"
#include "rsx_utils.h"
#include "rsx_decode.h"
#include "Emu/Cell/PPUCallback.h"
#include "Emu/Cell/lv2/sys_rsx.h"
#include "Capture/rsx_capture.h"
#include <thread>
template <>
void fmt_class_string<frame_limit_type>::format(std::string& out, u64 arg)
{
format_enum(out, arg, [](frame_limit_type value)
{
switch (value)
{
case frame_limit_type::none: return "Off";
case frame_limit_type::_59_94: return "59.94";
case frame_limit_type::_50: return "50";
case frame_limit_type::_60: return "60";
case frame_limit_type::_30: return "30";
case frame_limit_type::_auto: return "Auto";
}
return unknown;
});
}
namespace rsx
{
rsx_state method_registers;
std::array<rsx_method_t, 0x10000 / 4> methods{};
void invalid_method(thread* rsx, u32 _reg, u32 arg)
{
//Don't throw, gather information and ignore broken/garbage commands
//TODO: Investigate why these commands are executed at all. (Heap corruption? Alignment padding?)
LOG_ERROR(RSX, "Invalid RSX method 0x%x (arg=0x%x)", _reg << 2, arg);
rsx->invalid_command_interrupt_raised = true;
}
template<typename Type> struct vertex_data_type_from_element_type;
template<> struct vertex_data_type_from_element_type<float> { static const vertex_base_type type = vertex_base_type::f; };
template<> struct vertex_data_type_from_element_type<f16> { static const vertex_base_type type = vertex_base_type::sf; };
template<> struct vertex_data_type_from_element_type<u8> { static const vertex_base_type type = vertex_base_type::ub; };
template<> struct vertex_data_type_from_element_type<u16> { static const vertex_base_type type = vertex_base_type::s32k; };
template<> struct vertex_data_type_from_element_type<s16> { static const vertex_base_type type = vertex_base_type::s1; };
namespace nv406e
{
void set_reference(thread* rsx, u32 _reg, u32 arg)
{
rsx->sync();
rsx->ctrl->ref.exchange(arg);
}
void semaphore_acquire(thread* rsx, u32 /*_reg*/, u32 arg)
{
rsx->sync_point_request = true;
const u32 addr = get_address(method_registers.semaphore_offset_406e(), method_registers.semaphore_context_dma_406e());
// Get raw BE value
arg = be_t<u32>{arg}.raw();
const auto& sema = vm::_ref<nse_t<u32>>(addr);
// TODO: Remove vblank semaphore hack
if (sema == arg || addr == rsx->ctxt_addr + 0x30) return;
u64 start = get_system_time();
while (sema != arg)
{
if (Emu.IsStopped())
return;
if (const auto tdr = (u64)g_cfg.video.driver_recovery_timeout)
{
if (Emu.IsPaused())
{
while (Emu.IsPaused())
{
std::this_thread::sleep_for(1ms);
}
// Reset
start = get_system_time();
}
else
{
if ((get_system_time() - start) > tdr)
{
// If longer than driver timeout force exit
LOG_ERROR(RSX, "nv406e::semaphore_acquire has timed out. semaphore_address=0x%X", addr);
break;
}
}
}
rsx->on_semaphore_acquire_wait();
std::this_thread::yield();
}
rsx->performance_counters.idle_time += (get_system_time() - start);
}
void semaphore_release(thread* rsx, u32 _reg, u32 arg)
{
rsx->sync();
rsx->sync_point_request = true;
const u32 addr = get_address(method_registers.semaphore_offset_406e(), method_registers.semaphore_context_dma_406e());
if (LIKELY(g_use_rtm))
{
vm::write32(addr, arg);
}
else
{
auto& res = vm::reservation_lock(addr, 4);
vm::write32(addr, arg);
res &= -128;
}
if (addr >> 28 != 0x4)
{
vm::reservation_notifier(addr, 4).notify_all();
}
}
}
namespace nv4097
{
void clear(thread* rsx, u32 _reg, u32 arg)
{
// TODO: every backend must override method table to insert its own handlers
if (!rsx->do_method(NV4097_CLEAR_SURFACE, arg))
{
//
}
if (capture_current_frame)
{
rsx->capture_frame("clear");
}
}
void clear_zcull(thread* rsx, u32 _reg, u32 arg)
{
rsx->do_method(NV4097_CLEAR_ZCULL_SURFACE, arg);
if (capture_current_frame)
{
rsx->capture_frame("clear zcull memory");
}
}
void set_cull_face(thread* rsx, u32 reg, u32 arg)
{
switch(arg)
{
case CELL_GCM_FRONT_AND_BACK: return;
case CELL_GCM_FRONT: return;
case CELL_GCM_BACK: return;
default: break;
}
// Ignore value if unknown
method_registers.registers[reg] = method_registers.register_previous_value;
}
void set_notify(thread* rsx, u32 _reg, u32 arg)
{
const u32 location = method_registers.context_dma_notify();
const u32 index = (location & 0x7) ^ 0x7;
if ((location & ~7) != (CELL_GCM_CONTEXT_DMA_NOTIFY_MAIN_0 & ~7))
{
LOG_TRACE(RSX, "NV4097_NOTIFY: invalid context = 0x%x", method_registers.context_dma_notify());
return;
}
auto& notify = vm::_ref<RsxNotify>(verify(HERE, RSXIOMem.RealAddr(0xf100000 + (index * 0x40))));
notify.zero = 0;
notify.timestamp = rsx->timestamp();
}
void texture_read_semaphore_release(thread* rsx, u32 _reg, u32 arg)
{
// Pipeline barrier seems to be equivalent to a SHADER_READ stage barrier
// lle-gcm likes to inject system reserved semaphores, presumably for system/vsh usage
// Avoid calling render to avoid any havoc(flickering) they may cause from invalid flush/write
const u32 offset = method_registers.semaphore_offset_4097() & -16u;
if (offset > 63 * 4 && !rsx->do_method(NV4097_TEXTURE_READ_SEMAPHORE_RELEASE, arg))
{
//
}
auto& sema = vm::_ref<RsxSemaphore>(get_address(offset, method_registers.semaphore_context_dma_4097()));
sema.val = arg;
sema.pad = 0;
sema.timestamp = rsx->timestamp();
}
void back_end_write_semaphore_release(thread* rsx, u32 _reg, u32 arg)
{
// Full pipeline barrier
const u32 offset = method_registers.semaphore_offset_4097() & -16u;
if (offset > 63 * 4 && !rsx->do_method(NV4097_BACK_END_WRITE_SEMAPHORE_RELEASE, arg))
{
//
}
rsx->sync();
u32 val = (arg & 0xff00ff00) | ((arg & 0xff) << 16) | ((arg >> 16) & 0xff);
auto& sema = vm::_ref<RsxSemaphore>(get_address(offset, method_registers.semaphore_context_dma_4097()));
sema.val = val;
sema.pad = 0;
sema.timestamp = rsx->timestamp();
}
/**
* id = base method register
* index = register index in method
* count = element count per attribute
* register_count = number of registers consumed per attribute. E.g 3-element methods have padding
*/
template<u32 id, u32 index, int count, int register_count, typename type>
void set_vertex_data_impl(thread* rsx, u32 arg)
{
static const size_t increment_per_array_index = (register_count * sizeof(type)) / sizeof(u32);
static const size_t attribute_index = index / increment_per_array_index;
static const size_t vertex_subreg = index % increment_per_array_index;
const auto vtype = vertex_data_type_from_element_type<type>::type;
verify(HERE), vtype != rsx::vertex_base_type::cmp;
switch (vtype)
{
case rsx::vertex_base_type::ub:
case rsx::vertex_base_type::ub256:
// Get BE data
arg = be_t<u32>{arg}.raw();
break;
}
if (rsx->in_begin_end)
{
// Update to immediate mode register/array
rsx->append_to_push_buffer(attribute_index, count, vertex_subreg, vtype, arg);
// NOTE: one can update the register to update constant across primitive. Needs verification.
// Fall through
}
auto& info = rsx::method_registers.register_vertex_info[attribute_index];
info.type = vtype;
info.size = count;
info.frequency = 0;
info.stride = 0;
rsx::method_registers.register_vertex_info[attribute_index].data[vertex_subreg] = arg;
}
template<u32 index>
struct set_vertex_data4ub_m
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
set_vertex_data_impl<NV4097_SET_VERTEX_DATA4UB_M, index, 4, 4, u8>(rsx, arg);
}
};
template<u32 index>
struct set_vertex_data1f_m
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
set_vertex_data_impl<NV4097_SET_VERTEX_DATA1F_M, index, 1, 1, f32>(rsx, arg);
}
};
template<u32 index>
struct set_vertex_data2f_m
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
set_vertex_data_impl<NV4097_SET_VERTEX_DATA2F_M, index, 2, 2, f32>(rsx, arg);
}
};
template<u32 index>
struct set_vertex_data3f_m
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
//Register alignment is only 1, 2, or 4 (Rachet & Clank 2)
set_vertex_data_impl<NV4097_SET_VERTEX_DATA3F_M, index, 3, 4, f32>(rsx, arg);
}
};
template<u32 index>
struct set_vertex_data4f_m
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
set_vertex_data_impl<NV4097_SET_VERTEX_DATA4F_M, index, 4, 4, f32>(rsx, arg);
}
};
template<u32 index>
struct set_vertex_data2s_m
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
set_vertex_data_impl<NV4097_SET_VERTEX_DATA2S_M, index, 2, 2, u16>(rsx, arg);
}
};
template<u32 index>
struct set_vertex_data4s_m
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
set_vertex_data_impl<NV4097_SET_VERTEX_DATA4S_M, index, 4, 4, u16>(rsx, arg);
}
};
template<u32 index>
struct set_vertex_data_scaled4s_m
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
set_vertex_data_impl<NV4097_SET_VERTEX_DATA_SCALED4S_M, index, 4, 4, s16>(rsx, arg);
}
};
void set_array_element16(thread* rsx, u32, u32 arg)
{
if (rsx->in_begin_end)
{
rsx->append_array_element(arg & 0xFFFF);
rsx->append_array_element(arg >> 16);
}
}
void set_array_element32(thread* rsx, u32, u32 arg)
{
if (rsx->in_begin_end)
rsx->append_array_element(arg);
}
void draw_arrays(thread* rsx, u32 _reg, u32 arg)
{
rsx::method_registers.current_draw_clause.command = rsx::draw_command::array;
rsx::registers_decoder<NV4097_DRAW_ARRAYS>::decoded_type v(arg);
rsx::method_registers.current_draw_clause.append(v.start(), v.count());
}
void draw_index_array(thread* rsx, u32 _reg, u32 arg)
{
rsx::method_registers.current_draw_clause.command = rsx::draw_command::indexed;
rsx::registers_decoder<NV4097_DRAW_INDEX_ARRAY>::decoded_type v(arg);
rsx::method_registers.current_draw_clause.append(v.start(), v.count());
}
void draw_inline_array(thread* rsx, u32 _reg, u32 arg)
{
rsx::method_registers.current_draw_clause.command = rsx::draw_command::inlined_array;
rsx::method_registers.current_draw_clause.inline_vertex_array.push_back(arg);
}
template<u32 index>
struct set_transform_constant
{
static void impl(thread* rsxthr, u32 _reg, u32 arg)
{
static constexpr u32 reg = index / 4;
static constexpr u8 subreg = index % 4;
const u32 load = rsx::method_registers.transform_constant_load();
const u32 address = load + reg;
if (address >= 468)
{
// Ignore addresses outside the usable [0, 467] range
LOG_WARNING(RSX, "Invalid transform register index (load=%d, index=%d)", load, index);
return;
}
auto &value = rsx::method_registers.transform_constants[load + reg][subreg];
if (value != arg)
{
//Transform constants invalidation is expensive (~8k bytes per update)
value = arg;
rsxthr->m_graphics_state |= rsx::pipeline_state::transform_constants_dirty;
}
}
};
template<u32 index>
struct set_transform_program
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
if (rsx::method_registers.transform_program_load() >= 512)
{
// PS3 seems to allow exceeding the program buffer by upto 32 instructions before crashing
// Discard the "excess" instructions to not overflow our transform program buffer
// TODO: Check if the instructions in the overflow area are executed by PS3
LOG_WARNING(RSX, "Program buffer overflow!");
return;
}
method_registers.commit_4_transform_program_instructions(index);
rsx->m_graphics_state |= rsx::pipeline_state::vertex_program_dirty;
}
};
void set_transform_program_start(thread* rsx, u32 reg, u32)
{
if (method_registers.registers[reg] != method_registers.register_previous_value)
{
rsx->m_graphics_state |= rsx::pipeline_state::vertex_program_dirty;
}
}
void set_vertex_attribute_output_mask(thread* rsx, u32 reg, u32)
{
if (method_registers.registers[reg] != method_registers.register_previous_value)
{
rsx->m_graphics_state |= rsx::pipeline_state::vertex_program_dirty | rsx::pipeline_state::fragment_program_dirty;
}
}
void set_begin_end(thread* rsxthr, u32 _reg, u32 arg)
{
if (arg)
{
rsx::method_registers.current_draw_clause.reset(to_primitive_type(arg));
rsxthr->begin();
return;
}
//Check if we have immediate mode vertex data in a driver-local buffer
if (rsx::method_registers.current_draw_clause.command == rsx::draw_command::none)
{
const u32 push_buffer_vertices_count = rsxthr->get_push_buffer_vertex_count();
const u32 push_buffer_index_count = rsxthr->get_push_buffer_index_count();
//Need to set this flag since it overrides some register contents
rsx::method_registers.current_draw_clause.is_immediate_draw = true;
if (push_buffer_index_count)
{
rsx::method_registers.current_draw_clause.command = rsx::draw_command::indexed;
rsx::method_registers.current_draw_clause.append(0, push_buffer_index_count);
}
else if (push_buffer_vertices_count)
{
rsx::method_registers.current_draw_clause.command = rsx::draw_command::array;
rsx::method_registers.current_draw_clause.append(0, push_buffer_vertices_count);
}
}
else
rsx::method_registers.current_draw_clause.is_immediate_draw = false;
if (!rsx::method_registers.current_draw_clause.empty())
{
rsx::method_registers.current_draw_clause.compile();
rsxthr->end();
}
else
{
rsxthr->in_begin_end = false;
}
}
vm::addr_t get_report_data_impl(u32 offset)
{
u32 location = 0;
blit_engine::context_dma report_dma = method_registers.context_dma_report();
switch (report_dma)
{
case blit_engine::context_dma::to_memory_get_report: location = CELL_GCM_CONTEXT_DMA_REPORT_LOCATION_LOCAL; break;
case blit_engine::context_dma::report_location_main: location = CELL_GCM_CONTEXT_DMA_REPORT_LOCATION_MAIN; break;
case blit_engine::context_dma::memory_host_buffer: location = CELL_GCM_CONTEXT_DMA_MEMORY_HOST_BUFFER; break;
default:
return vm::addr_t(0);
}
return vm::cast(get_address(offset, location));
}
void get_report(thread* rsx, u32 _reg, u32 arg)
{
u8 type = arg >> 24;
u32 offset = arg & 0xffffff;
auto address_ptr = get_report_data_impl(offset);
if (!address_ptr)
{
LOG_ERROR(RSX, "Bad argument passed to NV4097_GET_REPORT, arg=0x%X", arg);
return;
}
vm::ptr<CellGcmReportData> result = address_ptr;
switch (type)
{
case CELL_GCM_ZPASS_PIXEL_CNT:
case CELL_GCM_ZCULL_STATS:
case CELL_GCM_ZCULL_STATS1:
case CELL_GCM_ZCULL_STATS2:
case CELL_GCM_ZCULL_STATS3:
rsx->get_zcull_stats(type, address_ptr);
break;
default:
LOG_ERROR(RSX, "NV4097_GET_REPORT: Bad type %d", type);
result->timer = rsx->timestamp();
result->padding = 0;
break;
}
}
void clear_report_value(thread* rsx, u32 _reg, u32 arg)
{
switch (arg)
{
case CELL_GCM_ZPASS_PIXEL_CNT:
case CELL_GCM_ZCULL_STATS:
break;
default:
LOG_ERROR(RSX, "NV4097_CLEAR_REPORT_VALUE: Bad type: %d", arg);
break;
}
rsx->clear_zcull_stats(arg);
}
void set_render_mode(thread* rsx, u32, u32 arg)
{
const u32 mode = arg >> 24;
switch (mode)
{
case 1:
rsx->conditional_render_enabled = false;
rsx->conditional_render_test_failed = false;
return;
case 2:
rsx->conditional_render_enabled = true;
LOG_WARNING(RSX, "Conditional rendering mode enabled (mode 2)");
break;
default:
rsx->conditional_render_enabled = false;
LOG_ERROR(RSX, "Unknown render mode %d", mode);
return;
}
const u32 offset = arg & 0xffffff;
auto address_ptr = get_report_data_impl(offset);
if (!address_ptr)
{
rsx->conditional_render_test_failed = false;
LOG_ERROR(RSX, "Bad argument passed to NV4097_SET_RENDER_ENABLE, arg=0x%X", arg);
return;
}
// Defer conditional render evaluation
rsx->sync_hint(FIFO_hint::hint_conditional_render_eval);
rsx->conditional_render_test_address = address_ptr;
rsx->conditional_render_test_failed = false;
}
void set_zcull_render_enable(thread* rsx, u32, u32 arg)
{
rsx->zcull_rendering_enabled = !!arg;
rsx->notify_zcull_info_changed();
}
void set_zcull_stats_enable(thread* rsx, u32, u32 arg)
{
rsx->zcull_stats_enabled = !!arg;
rsx->notify_zcull_info_changed();
}
void set_zcull_pixel_count_enable(thread* rsx, u32, u32 arg)
{
rsx->zcull_pixel_cnt_enabled = !!arg;
rsx->notify_zcull_info_changed();
}
void sync(thread* rsx, u32, u32)
{
rsx->sync();
}
void set_shader_program_dirty(thread* rsx, u32, u32)
{
rsx->m_graphics_state |= rsx::pipeline_state::fragment_program_dirty;
}
void set_surface_dirty_bit(thread* rsx, u32 reg, u32 arg)
{
if (reg == NV4097_SET_SURFACE_CLIP_VERTICAL ||
reg == NV4097_SET_SURFACE_CLIP_HORIZONTAL)
{
if (arg != method_registers.register_previous_value)
{
rsx->m_graphics_state |= rsx::pipeline_state::vertex_state_dirty;
}
}
rsx->m_rtts_dirty = true;
rsx->m_framebuffer_state_contested = false;
}
void set_surface_format(thread* rsx, u32 reg, u32 arg)
{
// Special consideration - antialiasing control can affect ROP state
const auto aa_mask = (0xF << 12);
if ((arg & aa_mask) != (method_registers.register_previous_value & aa_mask))
{
// Antialias control has changed, update ROP parameters
rsx->m_graphics_state |= rsx::pipeline_state::fragment_state_dirty;
}
set_surface_dirty_bit(rsx, reg, arg);
}
void set_surface_options_dirty_bit(thread* rsx, u32, u32)
{
if (rsx->m_framebuffer_state_contested)
rsx->m_rtts_dirty = true;
}
void set_ROP_state_dirty_bit(thread* rsx, u32, u32 arg)
{
if (arg != method_registers.register_previous_value)
{
rsx->m_graphics_state |= rsx::fragment_state_dirty;
}
}
void set_vertex_base_offset(thread* rsx, u32 reg, u32 arg)
{
if (rsx->in_begin_end &&
!rsx::method_registers.current_draw_clause.empty() &&
reg != method_registers.register_previous_value)
{
// Revert change to queue later
method_registers.decode(reg, method_registers.register_previous_value);
// Insert base mofifier barrier
method_registers.current_draw_clause.insert_command_barrier(vertex_base_modifier_barrier, arg);
}
}
void set_index_base_offset(thread* rsx, u32 reg, u32 arg)
{
if (rsx->in_begin_end &&
!rsx::method_registers.current_draw_clause.empty() &&
reg != method_registers.register_previous_value)
{
// Revert change to queue later
method_registers.decode(reg, method_registers.register_previous_value);
// Insert base mofifier barrier
method_registers.current_draw_clause.insert_command_barrier(index_base_modifier_barrier, arg);
}
}
void set_vertex_env_dirty_bit(thread* rsx, u32, u32 arg)
{
if (arg != method_registers.register_previous_value)
{
rsx->m_graphics_state |= rsx::pipeline_state::vertex_state_dirty;
}
}
void set_fragment_env_dirty_bit(thread* rsx, u32, u32 arg)
{
if (arg != method_registers.register_previous_value)
{
rsx->m_graphics_state |= rsx::pipeline_state::fragment_state_dirty;
}
}
void set_scissor_dirty_bit(thread* rsx, u32 reg, u32 arg)
{
if (arg != method_registers.register_previous_value)
{
rsx->m_graphics_state |= rsx::pipeline_state::scissor_config_state_dirty;
}
}
template<u32 index>
struct set_texture_dirty_bit
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
rsx->m_textures_dirty[index] = true;
if (rsx->current_fp_metadata.referenced_textures_mask & (1 << index))
{
rsx->m_graphics_state |= rsx::pipeline_state::fragment_program_dirty;
}
}
};
template<u32 index>
struct set_vertex_texture_dirty_bit
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
rsx->m_vertex_textures_dirty[index] = true;
if (rsx->current_vp_metadata.referenced_textures_mask & (1 << index))
{
rsx->m_graphics_state |= rsx::pipeline_state::vertex_program_dirty;
}
}
};
template<u32 index>
struct set_viewport_dirty_bit
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
if (arg != method_registers.register_previous_value)
{
rsx->m_graphics_state |= rsx::pipeline_state::vertex_state_dirty;
}
}
};
}
namespace nv308a
{
template<u32 index>
struct color
{
static void impl(thread* rsx, u32 _reg, u32 arg)
{
if (index >= method_registers.nv308a_size_out_x())
{
// Skip
return;
}
u32 color = arg;
u32 write_len = 4;
switch (method_registers.blit_engine_nv3062_color_format())
{
case blit_engine::transfer_destination_format::a8r8g8b8:
case blit_engine::transfer_destination_format::y32:
{
// Bit cast
break;
}
case blit_engine::transfer_destination_format::r5g6b5:
{
// Input is considered to be ARGB8
u32 r = (arg >> 16) & 0xFF;
u32 g = (arg >> 8) & 0xFF;
u32 b = arg & 0xFF;
r = u32(r * 32 / 255.f);
g = u32(g * 64 / 255.f);
b = u32(b * 32 / 255.f);
color = (r << 11) | (g << 5) | b;
write_len = 2;
break;
}
default:
{
fmt::throw_exception("Unreachable" HERE);
}
}
const u16 x = method_registers.nv308a_x();
const u16 y = method_registers.nv308a_y();
const u32 pixel_offset = (method_registers.blit_engine_output_pitch_nv3062() * y) + (x * write_len);
u32 address = get_address(method_registers.blit_engine_output_offset_nv3062() + pixel_offset + (index * write_len), method_registers.blit_engine_output_location_nv3062());
switch (write_len)
{
case 4:
vm::write32(address, color);
break;
case 2:
vm::write16(address, (u16)(color));
break;
default:
fmt::throw_exception("Unreachable" HERE);
}
rsx->m_graphics_state |= rsx::pipeline_state::fragment_program_dirty;
}
};
}
namespace nv3089
{
void image_in(thread *rsx, u32 _reg, u32 arg)
{
const rsx::blit_engine::transfer_operation operation = method_registers.blit_engine_operation();
const u16 out_x = method_registers.blit_engine_output_x();
const u16 out_y = method_registers.blit_engine_output_y();
const u16 out_w = method_registers.blit_engine_output_width();
const u16 out_h = method_registers.blit_engine_output_height();
const u16 in_w = method_registers.blit_engine_input_width();
const u16 in_h = method_registers.blit_engine_input_height();
const blit_engine::transfer_origin in_origin = method_registers.blit_engine_input_origin();
const blit_engine::transfer_interpolator in_inter = method_registers.blit_engine_input_inter();
rsx::blit_engine::transfer_source_format src_color_format = method_registers.blit_engine_src_color_format();
const f32 scale_x = method_registers.blit_engine_ds_dx();
const f32 scale_y = method_registers.blit_engine_dt_dy();
// NOTE: Do not round these value up!
// Sub-pixel offsets are used to signify pixel centers and do not mean to read from the next block (fill convention)
auto in_x = (u16)std::floor(method_registers.blit_engine_in_x());
auto in_y = (u16)std::floor(method_registers.blit_engine_in_y());
// Clipping
// Validate that clipping rect will fit onto both src and dst regions
const u16 clip_w = std::min(method_registers.blit_engine_clip_width(), out_w);
const u16 clip_h = std::min(method_registers.blit_engine_clip_height(), out_h);
// Check both clip dimensions and dst dimensions
if (clip_w == 0 || clip_h == 0)
{
LOG_WARNING(RSX, "NV3089_IMAGE_IN: Operation NOPed out due to empty regions");
return;
}
if (in_w == 0 || in_h == 0)
{
// Input cant be an empty region
fmt::throw_exception("NV3089_IMAGE_IN_SIZE: Invalid blit dimensions passed (in_w=%d, in_h=%d)" HERE, in_w, in_h);
}
u16 clip_x = method_registers.blit_engine_clip_x();
u16 clip_y = method_registers.blit_engine_clip_y();
//Fit onto dst
if (clip_x && (out_x + clip_x + clip_w) > out_w) clip_x = 0;
if (clip_y && (out_y + clip_y + clip_h) > out_h) clip_y = 0;
u16 in_pitch = method_registers.blit_engine_input_pitch();
switch (in_origin)
{
case blit_engine::transfer_origin::corner:
case blit_engine::transfer_origin::center:
break;
default:
LOG_WARNING(RSX, "NV3089_IMAGE_IN_SIZE: unknown origin (%d)", (u8)in_origin);
}
if (operation != rsx::blit_engine::transfer_operation::srccopy)
{
fmt::throw_exception("NV3089_IMAGE_IN_SIZE: unknown operation (%d)" HERE, (u8)operation);
}
const u32 src_offset = method_registers.blit_engine_input_offset();
const u32 src_dma = method_registers.blit_engine_input_location();
u32 dst_offset;
u32 dst_dma = 0;
rsx::blit_engine::transfer_destination_format dst_color_format;
u32 out_pitch = 0;
u32 out_alignment = 64;
switch (method_registers.blit_engine_context_surface())
{
case blit_engine::context_surface::surface2d:
{
dst_dma = method_registers.blit_engine_output_location_nv3062();
dst_offset = method_registers.blit_engine_output_offset_nv3062();
dst_color_format = method_registers.blit_engine_nv3062_color_format();
out_pitch = method_registers.blit_engine_output_pitch_nv3062();
out_alignment = method_registers.blit_engine_output_alignment_nv3062();
break;
}
case blit_engine::context_surface::swizzle2d:
{
dst_dma = method_registers.blit_engine_nv309E_location();
dst_offset = method_registers.blit_engine_nv309E_offset();
dst_color_format = method_registers.blit_engine_output_format_nv309E();
break;
}
default:
LOG_ERROR(RSX, "NV3089_IMAGE_IN_SIZE: unknown m_context_surface (0x%x)", (u8)method_registers.blit_engine_context_surface());
return;
}
const u32 in_bpp = (src_color_format == rsx::blit_engine::transfer_source_format::r5g6b5) ? 2 : 4; // bytes per pixel
const u32 out_bpp = (dst_color_format == rsx::blit_engine::transfer_destination_format::r5g6b5) ? 2 : 4;
if (out_pitch == 0)
{
out_pitch = out_bpp * out_w;
}
if (UNLIKELY(in_x == 1 || in_y == 1))
{
const bool is_graphics_op = scale_x < 0.f || scale_y < 0.f || in_bpp != out_bpp || fabsf(fabsf(scale_x * scale_y) - 1.f) > 0.000001f;
if (!is_graphics_op)
{
// No scaling factor, so size in src == size in dst
// Check for texel wrapping where (offset + size) > size by 1 pixel
// TODO: Should properly RE this behaviour when I have time (kd-11)
if (in_x == 1 && in_w == clip_w) in_x = 0;
if (in_y == 1 && in_h == clip_h) in_y = 0;
}
else
{
// Graphics operation, ignore subpixel correction offsets
if (in_x == 1) in_x = 0;
if (in_y == 1) in_y = 0;
}
}
const u32 in_offset = in_x * in_bpp + in_pitch * in_y;
const s32 out_offset = out_x * out_bpp + out_pitch * out_y;
const u32 src_address = get_address(src_offset, src_dma);
const u32 dst_address = get_address(dst_offset, dst_dma);
u8* pixels_src = vm::_ptr<u8>(src_address + in_offset);
u8* pixels_dst = vm::_ptr<u8>(dst_address + out_offset);
const auto read_address = get_address(src_offset, src_dma);
rsx->read_barrier(read_address, in_pitch * (in_h - 1) + (in_w * in_bpp));
if (dst_color_format != rsx::blit_engine::transfer_destination_format::r5g6b5 &&
dst_color_format != rsx::blit_engine::transfer_destination_format::a8r8g8b8)
{
fmt::throw_exception("NV3089_IMAGE_IN_SIZE: unknown dst_color_format (%d)" HERE, (u8)dst_color_format);
}
if (src_color_format != rsx::blit_engine::transfer_source_format::r5g6b5 &&
src_color_format != rsx::blit_engine::transfer_source_format::a8r8g8b8)
{
// Alpha has no meaning in both formats
if (src_color_format == rsx::blit_engine::transfer_source_format::x8r8g8b8)
{
src_color_format = rsx::blit_engine::transfer_source_format::a8r8g8b8;
}
else
{
// TODO: Support more formats
fmt::throw_exception("NV3089_IMAGE_IN_SIZE: unknown src_color_format (%d)" HERE, (u8)src_color_format);
}
}
u32 convert_w = (u32)(std::abs(scale_x) * in_w);
u32 convert_h = (u32)(std::abs(scale_y) * in_h);
if (convert_w == 0 || convert_h == 0)
{
LOG_ERROR(RSX, "NV3089_IMAGE_IN: Invalid dimensions or scaling factor. Request ignored (ds_dx=%f, dt_dy=%f)",
method_registers.blit_engine_ds_dx(), method_registers.blit_engine_dt_dy());
return;
}
if (!g_cfg.video.force_cpu_blit_processing && (dst_dma == CELL_GCM_CONTEXT_DMA_MEMORY_FRAME_BUFFER || src_dma == CELL_GCM_CONTEXT_DMA_MEMORY_FRAME_BUFFER))
{
blit_src_info src_info = {};
blit_dst_info dst_info = {};
src_info.format = src_color_format;
src_info.origin = in_origin;
src_info.width = in_w;
src_info.height = in_h;
src_info.pitch = in_pitch;
src_info.offset_x = in_x;
src_info.offset_y = in_y;
src_info.rsx_address = src_address;
src_info.pixels = pixels_src;
dst_info.format = dst_color_format;
dst_info.width = convert_w;
dst_info.height = convert_h;
dst_info.clip_x = clip_x;
dst_info.clip_y = clip_y;
dst_info.clip_width = clip_w;
dst_info.clip_height = clip_h;
dst_info.offset_x = out_x;