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interchange: pseudo pips: fix illegal tile pseudo PIPs #706

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merged 1 commit into from May 14, 2021

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acomodi
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@acomodi acomodi commented May 14, 2021

Signed-off-by: Alessandro Comodi acomodi@antmicro.com

This PR fixes chipsalliance/python-fpga-interchange#76. It allows to store site LUT-thrus that are used during site routing, so that, during the general routing step, the pseudo tile PIPs are correctly blocked by the lut equation.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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@gatecat gatecat left a comment

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LGTM

@gatecat gatecat merged commit 1b57679 into YosysHQ:master May 14, 2021
@acomodi acomodi deleted the fix-illegal-site-thru branch May 14, 2021 11:36
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Wrong LUT equation when used as LUT-thru
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