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Flattening failing #1641
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Thanks for your quick answer! I updated the script (and the repo) according to your advice. It appears than my top module "LMAC_CORE_TOP_SYNCH" is pushed down to "LMAC_CORE_TOP". |
Can you elaborate what you mean here? |
My top module is LMAC_CORE_TOP_SYNTH, it's just a wrapper of LMAC_CORE_TOP who's merging rclk and wclk into clk. |
BTW, about the |
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Looking again at the top module bug,
Seems like it is not parsing LMAC_CORE_TOP_SYNTH correctly, but something odd is going on as neither Verilator nor iverilog do either |
God knows where that file came from, but seems like the problem is some of the spaces are actually UTF-8 U+2008 "punctuation spaces" rather than normal ASCII ones.
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Just FYI, the code comes from one of the modules at https://github.com/lewiz-support |
I don't think the problematic file (LMAC_CORE_TOP_SYNTH) does - I'm mostly curious what kind of editor is actually inserting these characters... |
Dear community,
I encountered issues to flatten a design while I try to synthesize and techmap it with the latest version of Yosys. Design is dual-clock with a wrapper on top to merge read and write clocks. A small case works but the full design doesn't.
The issue appears at the first "synth" step using the flag "-flatten".
All the elements (scripts, netlits etc...) can be found at https://github.com/AurelienUoU/fifo_to_one_clock_dpram.git
Sincerely,
Aurelien
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