Several tests fail

[yurivict]

Version

0.22

Reproduction Steps

make test

Expected Behavior

n/a

Actual Behavior

Test: t_wide_read_a7r0w5b2 -> ok
Test: t_wide_write_a7r0w5b2 -> ok
gmake[2]: Leaving directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/tests/memlib'
cd tests/bram && bash run-test.sh ""
generating tests..
PRNG seed: 542627
running tests..
gmake[2]: Entering directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/tests/bram'
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 00_01.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 00_02.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 00_03.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 00_04.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 01_00.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 01_02.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 01_03.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 01_04.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 02_00.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 02_01.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 02_03.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 02_04.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 03_00.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 03_01.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 03_02.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 03_04.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 04_00.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 04_01.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 04_02.
../../techlibs/common/simlib.v:1378: warning: Port 1 (A) of $bmux expects 1 bits, got 32.
../../techlibs/common/simlib.v:1378:        : Pruning (signed) 31 high bits of the expression.
Passed memory_bram test 04_03.
gmake[2]: Leaving directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/tests/bram'
cd tests/various && bash run-test.sh
gmake[2]: Entering directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/tests/various'
Warning: Wire abc9_test027.$abc$91$o is used but has no driver.
Passed abc9.ys
Passed aiger_dff.ys
Passed attrib05_port_conn.ys
Passed attrib07_func_call.ys
Passed autoname.ys
Passed blackbox_wb.ys
Passed bug1496.ys
Passed bug1531.ys
Passed bug1614.ys
Passed bug1710.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
<<EOT:3: ERROR: syntax error, unexpected TOK_CONSTVAL
Expected error pattern 'syntax error, unexpected TOK_CONSTVAL' found !!!
Passed bug1745.ys
Passed bug1781.ys
Passed bug1876.ys
Passed bug2014.ys
Passed bug3462.ys
Passed const_arg_loop.ys
Passed const_func.ys
Passed const_func_block_var.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_BASE
Expected error pattern 'syntax error, unexpected TOK_BASE' found !!!
Passed constcomment.ys
Passed constmsk_test.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:3)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:4)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:5)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:6)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:7)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:8)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:9)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:10)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:11)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:12)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:13)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:14)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:15)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:52)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:53)
Passed countbits.ys
Passed deminout_unused.ys
Passed design.ys
ERROR: No saved design 'foo' found!
Expected error pattern 'No saved design 'foo' found!' found !!!
Passed design1.ys
ERROR: No saved design 'foo' found!
Expected error pattern 'No saved design 'foo' found!' found !!!
Passed design2.ys
Passed dynamic_part_select.ys
elab_sys_tasks.sv:8: Warning: X is 1.
elab_sys_tasks.sv:22: Warning: 
Passed elab_sys_tasks.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/share/simcells.v:456)
Passed equiv_opt_multiclock.ys
Passed equiv_opt_undef.ys
ERROR: Command stdout did have a line matching given regex "giraffe".
Expected error pattern 'stdout did have a line' found !!!
Passed exec.ys
Passed fib.ys
Passed fib_tern.ys
Passed func_port_implied_dir.ys
Passed gen_if_null.ys
Passed global_scope.ys
Passed gzip_verilog.ys
Passed help.ys
Passed hierarchy_defer.ys
Passed hierarchy_param.ys
Passed ice40_mince_abc9.ys
<<EOT:2: ERROR: syntax error, unexpected '[', expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
Expected error pattern 'syntax error, unexpected' found !!!
Passed integer_range_bad_syntax.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_REAL, expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
Expected error pattern 'syntax error, unexpected TOK_REAL' found !!!
Passed integer_real_bad_syntax.ys
attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033"
Passed json_escape_chars.ys
ERROR: Identifier `\b' is implicitly declared.
Expected error pattern 'is implicitly declared.' found !!!
Passed logger_error.ys
Passed logger_nowarning.ys
Warning: Found log message matching -W regex:
Added regex 'Successfully finished Verilog frontend.' for warnings to expected warning list.
<<EOF:2: Warning: Identifier `\b' is implicitly declared.
<<EOF:2: Warning: Identifier `\w' is implicitly declared.
Warning: Found log message matching -W regex:
Successfully finished Verilog frontend.
Passed logger_warn.ys
<<EOF:2: Warning: Identifier `\b' is implicitly declared.
<<EOF:2: Warning: Identifier `\w' is implicitly declared.
Passed logger_warning.ys
Passed logic_param_simple.ys
Passed mem2reg.ys
Passed memory_word_as_index.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/share/simcells.v:456)
Passed muxcover.ys
Passed muxpack.ys
Passed param_struct.ys
Passed peepopt.ys
Passed pmgen_reduce.ys
Passed pmux2shiftx.ys
Warning: Resizing cell port act.ou2.out from 3 bits to 2 bits.
Warning: Resizing cell port act.os2.out from 3 bits to 2 bits.
Warning: Resizing cell port act.ou1.out from 3 bits to 1 bits.
Warning: Resizing cell port act.os1.out from 3 bits to 1 bits.
Warning: Resizing cell port act.pt9.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt7.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt6.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt5.a from 2 bits to 4 bits.
Warning: Resizing cell port act.pt4.a from 1 bits to 4 bits.
Warning: Resizing cell port act.pt3.a from 1 bits to 4 bits.
Warning: Resizing cell port act.pt2.a from 1 bits to 4 bits.
Passed port_sign_extend.ys
Passed primitives.ys
Passed printattr.ys
Passed rand_const.ys
Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26.9-26.21.
Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29.3-29.18.
Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35.8-35.22.
Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62.3-62.16.
Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69.3-69.17.
Warning: Replacing memory \ml3 with list of registers. See reg_wire_error.sv:70
Warning: Replacing memory \mr3 with list of registers. See reg_wire_error.sv:68
Warning: Replacing memory \ml2 with list of registers. See reg_wire_error.sv:63
Warning: Replacing memory \mr2 with list of registers. See reg_wire_error.sv:61
Warning: Replacing memory \ml1 with list of registers. See reg_wire_error.sv:58
Passed reg_wire_error.ys
Passed rename_scramble_name.ys
Passed scratchpad.ys
Passed script.ys
Passed sformatf.ys
Passed shregmap.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_INTEGER, expecting TOK_ID or '['
Expected error pattern 'syntax error, unexpected TOK_INTEGER' found !!!
Passed signed.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:4)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:5)
Passed signext.ys
Passed sim_const.ys
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MIN = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_TYP = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MAX = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MIN = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_TYP = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MAX = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MIN = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_TYP = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MAX = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MIN = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_TYP = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MAX = 1.500000 with string.
Warning: No SAT model available for cell B_0 ($specrule).
Warning: No SAT model available for cell A_0 ($specify3).
Warning: No SAT model available for cell C_0 ($specrule).
Warning: No SAT model available for cell A_0 ($specify2).
Warning: No SAT model available for cell B_0 ($specify2).
Passed specify.ys
Warning: wire '\o' is assigned in a block at <<EOT:2.11-2.17.
Warning: wire '\p' is assigned in a block at <<EOT:3.11-3.16.
Passed src.ys
Warning: Critical-path does not terminate in a recognised endpoint.
Warning: Cell type 'const0' not recognised! Ignoring.
Passed sta.ys
Passed struct_access.ys
Warning: Port directions for cell \s1 (\DFF) are unknown. Assuming inout for all ports.
Warning: Port directions for cell \s2 (\DFF) are unknown. Assuming inout for all ports.
Warning: Port directions for cell \s3 (\DFF) are unknown. Assuming inout for all ports.
Passed submod.ys
Passed submod_extract.ys
Passed sv_defines.ys
ERROR: Duplicate macro arguments with name `x'.
Expected error pattern 'Duplicate macro arguments with name `x'' found !!!
Passed sv_defines_dup.ys
ERROR: Mismatched brackets in macro argument: [ and }.
Expected error pattern 'Mismatched brackets in macro argument: \[ and }.' found !!!
Passed sv_defines_mismatch.ys
ERROR: Cannot expand macro `foo by giving only 1 argument (argument 2 has no default).
Expected error pattern 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' found !!!
Passed sv_defines_too_few.ys
Passed wreduce.ys
Passed write_gzip.ys
Passed xaiger.ys
Passed async.sh
Passed chparam.sh
Passed hierarchy.sh
Passed logger_fail.sh
Passed plugin.sh
Passed smtlib2_module.sh
Passed sv_implicit_ports.sh
Passed svalways.sh
gmake[2]: Leaving directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/tests/various'
cd tests/select && bash run-test.sh
Running blackboxes.ys..
Running no_warn_assert.ys..
Running no_warn_prefixed_arg_memb.ys..
Running no_warn_prefixed_empty_select_arg.ys..
Running unset.ys..
ERROR: Selection '\foo' does not exist!
Expected error pattern 'Selection '\\foo' does not exist!' found !!!
Running unset2.ys..
ERROR: Selection @foo is not defined!
Expected error pattern 'Selection @foo is not defined!' found !!!
Running warn_empty_select_arg.ys..
Warning: Selection "foo" did not match any module.
Warning: Selection "bar" did not match any object.
cd tests/sat && bash run-test.sh
gmake[2]: Entering directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/tests/sat'
Passed asserts.ys
Passed asserts_seq.ys
Passed bug2595.ys
Warning: Complex async reset for dff `\q [12]'.
Warning: Complex async reset for dff `\q [8]'.
Passed clk2fflogic.ys
Passed counters-repeat.ys
Passed counters.ys
Passed dff.ys
Passed expose_dff.ys
ERROR: Error opening 'grom.fst' as FST file
gmake[2]: *** [run-test.mk:46: grom.ys] Error 1
gmake[2]: Leaving directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22/tests/sat'
gmake[1]: *** [Makefile:831: test] Error 2
gmake[1]: Leaving directory '/disk-samsung/freebsd-ports/cad/yosys/work/yosys-yosys-0.22'
*** Error code 1

[lethalbit]

I suspect this to be a FreeBSD related issue, as it doesn't seem to happen on our CI, nor can I reproduce it locally on my own system.

I'll set up a FreeBSD VM to test in when I have a chance to see if I can reproduce it then.

[lparkes]

FYI I see this same error on NetBSD when compiling with clang. (Compiling Yosys with GCC on NetBSD doesn't get this far through the tests).

[lparkes]

I have zeroed in on the code in libs/fst/fstapi.cc:fstReaderInit() where it starts with "if (zhandle)". About line 4276.

So what appears to be happening on NetBSD is that the initial read of grom.fst via stdio is buffered and so even though ftell() reports that file position is 17, the seek position of the underlying file descriptor is 905 (the end of the file). The file descriptor is then dup()ed and the new file descriptor's seek position is shared with the original file descriptor and so it is still 905.

gzread() then has nothing to read because we are at EOF.

I added the line "lseek(zfd, ftell(xc->f), SEEK_SET);" just after line 4274 so that the new file descriptor was positioned where we have asked stdio to read upto.

This unit test still doesn't work, but at least it doesn't exit after failing to read the FST file.

[lparkes]

I think I've fixed this and I've created PR #3512 for it. It's just two lines of code.

[mmicko]

Fixed with #3512