[Meta/tracking/discussion issue] Better support for "real-life" sum-of-product architectures

[ArcaneNibble]

Currently, yosys has the abc -sop command to turn the combinatorial parts of a design into $sop sum-of-product cells. This command has two important parameters: -I controls the maximum number of inputs into a $sop cell, and -P controls the maximum number of product terms in a $sop cell. Although this is perfect for "classic" sum-of-product devices like the 20V8 in "simple" mode, issues arise with newer devices that have more features. This is intended to be a tracking issue to discuss how to tackle these problems. For the projects that I am working on, issue 2 below is the highest priority, and issues 4 and 5 are low priority. However, I'm listing all of these issues at once in case there is a generic solution that can apply to multiple of them.

1. Different number of product terms available in different macrocells

The 20V8 in registered mode supports 8 product terms per macrocell if the macrocell is registered but only 7 product terms per macrocell if the macrocell is combinatorial (one product term is taken for controlling the output enable). The 22V10 has some macrocells that only have 8 product terms while some other macrocells have 10, 12, 14, or 16. Assuming that the pinout has not been constrained yet, it would be nice if yosys could somehow figure out which parts of the design require more product terms and assign those parts of the design to the macrocells with the larger number of product terms.

One possible approach to this problem is to use something like (for the 22V10) abc -sop -P 16 -I 22 and then raise an error if all of the resulting $sop cells do not actually fit in the device. For example, an error would be raised if more than two $sop cells end up requiring more than 16 product terms. However, this is suboptimal because, if the chip isn't full, it should be possible to take some of the $sop cells that are too big and "break them up" into a cascade of $sop cells that do fit in the device. The question then becomes "how do we choose which cells to break up?" and "how do we do this efficiently?"

2. Additional gates at the output of the sum-of-products

Many CPLDs (as opposed to "classic" PALs/GALs) have an XOR gate at the output of each sum-of-products that can XOR the output of the sum-of-products with an additional product term (e.g. a logic equation like (ab + cd) ^ e). For example, the XC9500/XC9500XL, MAX 7000, and Coolrunner-II all have an XOR gate like this. The Xilinx XPLA3 is more powerful and has a LUT2 rather than a simple XOR. Although abc supports a mode that can synthesize the design into ESOP (exclusive-sum-of-products) form, there doesn't seem to be an obvious way to handle this "only one XOR at the output" architecture. This is important for getting reasonable-sized counters and adders.

3. PLA architectures as opposed to PAL architectures

Some devices like the Xilinx XPLA3 or Coolrunner-II use a PLA architecture rather than a PAL architecture. This means that they have a variable number of product terms available to each macrocell rather than a fixed number. (E.g. in a 22V10 each sum-of-products can have only 8/10/12/14/16 product terms and that's it. However, in a Coolrunner-II, the macrocells in a "function block" all share the same pool of 54 product terms.) It would be nice if abc could somehow know about this and try and reuse product terms if possible. However, it is not yet known how much this would actually help in reality.

4. Foldback NAND gates

Some devices like the Xilinx XPLA3 have "foldback NAND gates." These are essentially product terms that feed into an inverter that then feeds back into an input into the sum-of-products matrix. These gates are supposedly useful for creating effectively-wider sum terms. It would be nice if yosys could use these, but it is unclear how to take advantage of these (even Phillips, the original(?) inventor of this architecture, supposedly had difficulty making generic logic synthesis take advantage of these foldback NANDs).

5. "Extra" AND functionality

Some devices like the Xilinx XC9500 can perform a wired-AND of input pins before feeding the AND-ed signal into the sum-of-products array. This can give each sum-of-products an effectively-larger number of inputs. It would be nice if yosys could use these, but it is unclear how to take advantage of these.