Galois Counter Mode AES Encryption in Verilog and Software Test Tool

GCM-AES implementation in Verilog

This is a "pipelined" version of hardware implementaion in system-verilog. Here I pipeline the key expansion process into 15 steps to address the SLACK problem. This implements encryption in 110MHz. Throughput is 2 * 128bits * 200M = 51.2 Gbps. Worst SLACK is 0.04 ns. Reference AES.

Usage

Requirement:

Vivado 16.4 or higher.
Implementaion is on a SUME FPGA board.

Simulation:

Modify the simulation file test128.sv.
In the directory run:

bash shell/sim.bash

Implementation

Run:

bash shell/make.bash

Download the bitstream file to hardware.
ATTENTION It is a real-time running version of 128 bit encryption which only supports 128-bit-multiple input by now.

Software validation is in the pyaes repository

Usage

Run:

cd pyaes
ipython3 notebook

Modify and run the pyaes\test.py to get the right encryption result for 128-bit-mulitple input. Or you can migrate to ipython notebook to debug it. And modify the input in test128.sv to check if the SW/HW results coincide.

TODO:

(Now 15 clks) Further parallelize the data links.
(Done encryption part) Double the data rate by using data on falling and rising edge.

Name		Name	Last commit message	Last commit date
Latest commit History 102 Commits
fsm		fsm
pyaes		pyaes
pytest		pytest
reports		reports
shell		shell
.gitignore		.gitignore
.vimrc		.vimrc
README.md		README.md
aes_api.v		aes_api.v
aes_key_gen.sv		aes_key_gen.sv
aes_pipeline_stage1.sv		aes_pipeline_stage1.sv
aes_pipeline_stage10.sv		aes_pipeline_stage10.sv
aes_pipeline_stage2.sv		aes_pipeline_stage2.sv
aes_pipeline_stage2_pre.sv		aes_pipeline_stage2_pre.sv
aes_pipeline_stage3.sv		aes_pipeline_stage3.sv
aes_pipeline_stage3_pre.sv		aes_pipeline_stage3_pre.sv
aes_pipeline_stage4.sv		aes_pipeline_stage4.sv
aes_pipeline_stage4_pre.sv		aes_pipeline_stage4_pre.sv
aes_pipeline_stage5.sv		aes_pipeline_stage5.sv
aes_pipeline_stage5_pre.sv		aes_pipeline_stage5_pre.sv
aes_pipeline_stage6.sv		aes_pipeline_stage6.sv
aes_pipeline_stage6_pre.sv		aes_pipeline_stage6_pre.sv
aes_pipeline_stage7.sv		aes_pipeline_stage7.sv
aes_pipeline_stage7_pre.sv		aes_pipeline_stage7_pre.sv
aes_pipeline_stage8.sv		aes_pipeline_stage8.sv
aes_pipeline_stage9.sv		aes_pipeline_stage9.sv
aes_signal_passing.sv		aes_signal_passing.sv
build_project.tcl		build_project.tcl
bypasser.sv		bypasser.sv
bypasswriter.py		bypasswriter.py
clk_gen.sv		clk_gen.sv
compile.tcl		compile.tcl
constraints_artix_7.xdc		constraints_artix_7.xdc
fn_aes_encrypt_stage.sv		fn_aes_encrypt_stage.sv
fn_aes_ghash_multiplication.sv		fn_aes_ghash_multiplication.sv
fn_aes_key_expansion.sv		fn_aes_key_expansion.sv
gcm_aes.sv		gcm_aes.sv
phase_bypasser.sv		phase_bypasser.sv
simulate.tcl		simulate.tcl
syn_impl_blog.txt		syn_impl_blog.txt
test128.sv		test128.sv
text_bypasser.sv		text_bypasser.sv
version.txt		version.txt

Yucao42/AES_GCM

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Galois Counter Mode AES Encryption in Verilog and Software Test Tool

GCM-AES implementation in Verilog

Usage

Requirement:

Simulation:

Implementation

Software validation is in the pyaes repository

Usage

TODO:

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