enable/disable interrupt functions for avr and riscv

ZigEmbeddedGroup · Apr 26, 2023 · 70b1cb0 · 70b1cb0
1 parent 54c6cbe
commit 70b1cb0
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/src/modules/cpus/avr5.zig b/src/modules/cpus/avr5.zig
@@ -2,11 +2,11 @@ const std = @import("std");
 const microzig = @import("microzig");
 const root = @import("root");
 
-pub inline fn sei() void {
+pub fn enable_interrupts() void {
     asm volatile ("sei");
 }
 
-pub inline fn cli() void {
+pub fn disable_interrupts() void {
     asm volatile ("cli");
 }
 

diff --git a/src/modules/cpus/riscv32.zig b/src/modules/cpus/riscv32.zig
@@ -2,11 +2,11 @@ const std = @import("std");
 const root = @import("root");
 const microzig = @import("microzig");
 
-pub fn sei() void {
+pub fn enable_interrupts() void {
     // asm volatile ("sei");
 }
 
-pub fn cli() void {
+pub fn disable_interrupts() void {
     // asm volatile ("cli");
 }