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flexpress.txt
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flexpress.txt
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################################################################################
##
## Filename: flexpress.txt
## {{{
## Project: ArrowZip, a demonstration of the Arrow MAX1000 FPGA board
##
## Purpose: Describes the flash in our new data format.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2021, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
################################################################################
##
## }}}
@PREFIX=flash
@DEVID=FLASH
@$LGFLASHSZ=23
@$NADDR=(1<<(@$LGFLASHSZ-2))
@$NBYTES=(1<<@$LGFLASHSZ)
@NBYTES.FORMAT=0x%08x
@ACCESS=@$(DEVID)_ACCESS
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wb
@LD.PERM=rx
@TOP.PORTLIST=
// Top level Dual-SPI I/O ports
o_dspi_cs_n, o_dspi_sck, io_dspi_dat
@TOP.IODECL=
// Dual SPI flash
output wire o_dspi_cs_n;
output wire o_dspi_sck;
inout wire [1:0] io_dspi_dat;
@TOP.DEFNS=
wire w_dspi_cs_n, w_dspi_sck;
wire [1:0] dspi_bmod, i_dspi_dat, dspi_datp, dspi_datn, o_dspi_dat;
@TOP.MAIN=
// Dual SPI flash
w_dspi_cs_n, w_dspi_sck, o_dspi_dat, i_dspi_dat, dspi_bmod
@TOP.INSERT=
//
//
// Wires for setting up the QSPI flash wishbone peripheral
//
//
// QSPI)BMOD, Dual SPI bus mode, Bus modes are:
// 0? Normal serial mode, one bit in one bit out
// 10 Dual SPI mode, going out
// 11 Dual SPI mode coming from the device (read mode)
yaddro dspi_ddr_csn( .i_clk(s_clk),
.i_data({(2){ w_dspi_cs_n}}), .o_pad(o_dspi_cs_n));
yaddro dspi_ddr_sck( .i_clk(s_clk),
.i_data({(2){w_dspi_sck}}), .o_pad(o_dspi_sck));
yaddrio dspi_d0(.i_clk(s_clk),
.i_we(!dspi_bmod[0]),
.i_data({(2){o_dspi_dat[0]}}),
.o_data({dspi_datp[0], dspi_datn[0]}),
.io_pad(io_dspi_dat[0]));
yaddrio dspi_d1(.i_clk(s_clk),
.i_we((dspi_bmod == 2'b10)?1'b1:1'b0),
.i_data({(2){o_dspi_dat[1]}}),
.o_data({dspi_datp[1], dspi_datn[1]}),
.io_pad(io_dspi_dat[1]));
assign i_dspi_dat = dspi_datn;
@MAIN.PORTLIST=
// The Universal DSPI Flash
o_dspi_cs_n, o_dspi_sck, o_dspi_dat, i_dspi_dat, o_dspi_mod
@MAIN.IODECL=
// The QSPI flash
output wire o_dspi_cs_n;
output wire o_dspi_sck;
output wire [1:0] o_dspi_dat;
input wire [1:0] i_dspi_dat;
output wire [1:0] o_dspi_mod;
@MAIN.DEFNS=
// Definitions for the @$(PREFIX) debug port
wire @$(PREFIX)_dbg_trigger;
wire [31:0] @$(PREFIX)_debug;
@MAIN.INSERT=
dualflexpress #(.LGFLASHSZ(@$LGFLASHSZ),
.RDDELAY(2), .OPT_CLKDIV(1), .NDUMMY(4),
`ifdef FLASHCFG_ACCESS
.OPT_CFG(1'b1))
`else
.OPT_CFG(1'b0))
`endif
@$(PREFIX)i(i_clk, i_reset,
(wb_cyc), (wb_stb)&&(@$(PREFIX)_sel),
(wb_stb)&&(flashcfg_sel), wb_we,
wb_addr[(@$LGFLASHSZ-3):0], wb_data,
@$(PREFIX)_ack, @$(PREFIX)_stall, @$(PREFIX)_data,
o_dspi_sck, o_dspi_cs_n, o_dspi_mod, o_dspi_dat, i_dspi_dat,
@$(PREFIX)_dbg_trigger, @$(PREFIX)_debug);
@MAIN.ALT=
assign o_dspi_sck = 1'b0;
assign o_dspi_cs_n = 1'b1;
assign o_dspi_mod = 2'b01;
assign o_dspi_dat = 2'b11;
@MEM.NAME= flash
@MEM.ACCESS = rx
@REGS.N= 1
@REGDEFS.H.DEFNS=
#define DSPI_FLASH
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$NBYTES
#define @$(DEVID)LGLEN @$LGFLASHSZ
@REGS.0= 0 R_@$(DEVID) FLASH
@BDEF.OSDEF=_BOARD_HAS_FLASH
@BDEF.OSVAL=extern char _@$(PREFIX)[@$NBYTES];
@LDSCRIPT.PSTR= rx
@LDSCRIPT.PTR= @$(PREFIX)
@LDSCRIPT.DEF=
_@$(PREFIX)=ORIGIN(@$(PREFIX));
@REGDEFS.H.INSERT=
@SIM.INCLUDE=
#include "flashsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
FLASHSIM *m_@$(MEM.NAME);
unsigned m_last_dspi_dat;
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_@$(MEM.NAME) = new FLASHSIM(FLASHLGLEN);
m_last_dspi_dat = 15;
#endif // @$(ACCESS)
@SIM.TICK=
#ifdef @$(ACCESS)
m_core->i_dspi_dat = m_@$(MEM.NAME)->simtick(
m_core->o_dspi_cs_n,
m_core->o_dspi_sck,
m_core->o_dspi_dat,
(m_core->o_dspi_mod&1)|((m_core->o_dspi_mod&2)<<1));
m_core->i_dspi_dat &= 0x03;
#endif // @$(ACCESS)
@SIM.LOAD=
#ifdef @$(ACCESS)
m_@$(MEM.NAME)->load(start, &buf[offset], wlen);
#endif // @$(ACCESS)
##
##
##
##
## Now the control interface
@PREFIX=flashcfg
@NADDR=1
@DEVID=FLASHCFG
@ACCESS=@$(DEVID)_ACCESS
@DEPENDS= FLASH_ACCESS
## Although this is really a SLAVE.TYPE=SINGLE interface, it receives its
## acknowledgements from the flash above. SLAVE.TYPE=SINGLE will create
## acknowledgements in the interconnect, resulting in bus errors. As a result,
## this must be a SLAVE.TYPE=OTHER
##
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb
@MAIN.INSERT=
// The Flash control interface result comes back together with the
// flash interface itself. Hence, we always return zero here.
assign @$(PREFIX)_ack = 1'b0;
assign @$(PREFIX)_stall = 1'b0;
assign @$(PREFIX)_data = flash_data;
@REGS.NOTE= // FLASH erase/program configuration registers
@REGS.N= 1
@REGS.0= 0 R_@$(DEVID) @$(DEVID) QSPIC
@REGDEFS.H.INSERT=
// Flash control constants
#define DSPI_FLASH // This core and hardware support a Dual SPI flash
#define SZPAGEB 256
#define PGLENB 256
#define SZPAGEW 64
#define PGLENW 64
#define NPAGES 256
#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
#define SECTORSZW (NPAGES * SZPAGEW) // In words
#define NSECTORS 64
#define SECTOROF(A) ((A) & (-1<<16))
#define SUBSECTOROF(A) ((A) & (-1<<12))
#define PAGEOF(A) ((A) & (-1<<8))
@BDEF.IONAME= _@$(PREFIX)
@BDEF.OSDEF= _BOARD_HAS_@$(DEVID)
@BDEF.IOTYPE=unsigned
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) * const @$(BDEF.IONAME) = ((@$BDEF.IOTYPE *)(@$[0x%08x](REGBASE)));
##
@RTL.MAKE.GROUP= FLASH
@RTL.MAKE.FILES= dualflexpress.v