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  • Gisselquist Technology, LLC

Pinned repositories

  1. openarty

    An Open Source configuration of the Arty platform

    Verilog 44 9

  2. s6soc

    CMod-S6 SoC

    Verilog 18 3

  3. wb2axip

    A pipelined wishbone to AXI converter

    Verilog 19 1

  4. wbuart32

    A simple UART controller that can easily be wishbone controlled.

    Verilog 34 11

  5. zipcpu

    A small, light weight, RISC CPU soft core

    Verilog 239 22

  6. autofpga

    A utility for Composing FPGA designs from Peripherals

    C++ 42 4

739 contributions in the last year

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Contribution activity

October 2018

Created an issue in YosysHQ/yosys that received 1 comment

Yosys does not support $changed

$changed(X) is defined in SVA to be equivalent to (A != $past(A)); Steps to reproduce the issue The following code, always @(posedge i_clk) if (f_p…

1 comment

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