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assembler_aarch64.hpp
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assembler_aarch64.hpp
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/*
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
#define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
#include "asm/register.hpp"
#include "metaprogramming/enableIf.hpp"
#ifdef __GNUC__
// __nop needs volatile so that compiler doesn't optimize it away
#define NOP() asm volatile ("nop");
#elif defined(_MSC_VER)
// Use MSVC instrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
#define NOP() __nop();
#endif
// definitions of various symbolic names for machine registers
// First intercalls between C and Java which use 8 general registers
// and 8 floating registers
// we also have to copy between x86 and ARM registers but that's a
// secondary complication -- not all code employing C call convention
// executes as x86 code though -- we generate some of it
class Argument {
public:
enum {
n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
};
};
REGISTER_DECLARATION(Register, c_rarg0, r0);
REGISTER_DECLARATION(Register, c_rarg1, r1);
REGISTER_DECLARATION(Register, c_rarg2, r2);
REGISTER_DECLARATION(Register, c_rarg3, r3);
REGISTER_DECLARATION(Register, c_rarg4, r4);
REGISTER_DECLARATION(Register, c_rarg5, r5);
REGISTER_DECLARATION(Register, c_rarg6, r6);
REGISTER_DECLARATION(Register, c_rarg7, r7);
REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
// Symbolically name the register arguments used by the Java calling convention.
// We have control over the convention for java so we can do what we please.
// What pleases us is to offset the java calling convention so that when
// we call a suitable jni method the arguments are lined up and we don't
// have to do much shuffling. A suitable jni method is non-static and a
// small number of arguments
//
// |--------------------------------------------------------------------|
// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
// |--------------------------------------------------------------------|
// | r0 r1 r2 r3 r4 r5 r6 r7 |
// |--------------------------------------------------------------------|
// | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
// |--------------------------------------------------------------------|
REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
// Java floating args are passed as per C
REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
// registers used to hold VM data either temporarily within a method
// or across method calls
// volatile (caller-save) registers
// r8 is used for indirect result location return
// we use it and r9 as scratch registers
REGISTER_DECLARATION(Register, rscratch1, r8);
REGISTER_DECLARATION(Register, rscratch2, r9);
// current method -- must be in a call-clobbered register
REGISTER_DECLARATION(Register, rmethod, r12);
// non-volatile (callee-save) registers are r16-29
// of which the following are dedicated global state
// link register
REGISTER_DECLARATION(Register, lr, r30);
// frame pointer
REGISTER_DECLARATION(Register, rfp, r29);
// current thread
REGISTER_DECLARATION(Register, rthread, r28);
// base of heap
REGISTER_DECLARATION(Register, rheapbase, r27);
// constant pool cache
REGISTER_DECLARATION(Register, rcpool, r26);
// monitors allocated on stack
REGISTER_DECLARATION(Register, rmonitors, r25);
// locals on stack
REGISTER_DECLARATION(Register, rlocals, r24);
// bytecode pointer
REGISTER_DECLARATION(Register, rbcp, r22);
// Dispatch table base
REGISTER_DECLARATION(Register, rdispatch, r21);
// Java stack pointer
REGISTER_DECLARATION(Register, esp, r20);
// Preserved predicate register with all elements set TRUE.
REGISTER_DECLARATION(PRegister, ptrue, p7);
#define assert_cond(ARG1) assert(ARG1, #ARG1)
namespace asm_util {
uint32_t encode_logical_immediate(bool is32, uint64_t imm);
uint32_t encode_sve_logical_immediate(unsigned elembits, uint64_t imm);
bool operand_valid_for_immediate_bits(int64_t imm, unsigned nbits);
};
using namespace asm_util;
class Assembler;
class Instruction_aarch64 {
unsigned insn;
#ifdef ASSERT
unsigned bits;
#endif
Assembler *assem;
public:
Instruction_aarch64(class Assembler *as) {
#ifdef ASSERT
bits = 0;
#endif
insn = 0;
assem = as;
}
inline ~Instruction_aarch64();
unsigned &get_insn() { return insn; }
#ifdef ASSERT
unsigned &get_bits() { return bits; }
#endif
static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
union {
unsigned u;
int n;
};
u = val << (31 - hi);
n = n >> (31 - hi + lo);
return n;
}
static inline uint32_t extract(uint32_t val, int msb, int lsb) {
int nbits = msb - lsb + 1;
assert_cond(msb >= lsb);
uint32_t mask = checked_cast<uint32_t>(right_n_bits(nbits));
uint32_t result = val >> lsb;
result &= mask;
return result;
}
static inline int32_t sextract(uint32_t val, int msb, int lsb) {
uint32_t uval = extract(val, msb, lsb);
return extend(uval, msb - lsb);
}
static void patch(address a, int msb, int lsb, uint64_t val) {
int nbits = msb - lsb + 1;
guarantee(val < (1ULL << nbits), "Field too big for insn");
assert_cond(msb >= lsb);
unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
val <<= lsb;
mask <<= lsb;
unsigned target = *(unsigned *)a;
target &= ~mask;
target |= val;
*(unsigned *)a = target;
}
static void spatch(address a, int msb, int lsb, int64_t val) {
int nbits = msb - lsb + 1;
int64_t chk = val >> (nbits - 1);
guarantee (chk == -1 || chk == 0, "Field too big for insn");
unsigned uval = val;
unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
uval &= mask;
uval <<= lsb;
mask <<= lsb;
unsigned target = *(unsigned *)a;
target &= ~mask;
target |= uval;
*(unsigned *)a = target;
}
void f(unsigned val, int msb, int lsb) {
int nbits = msb - lsb + 1;
guarantee(val < (1ULL << nbits), "Field too big for insn");
assert_cond(msb >= lsb);
val <<= lsb;
insn |= val;
#ifdef ASSERT
unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
mask <<= lsb;
assert_cond((bits & mask) == 0);
bits |= mask;
#endif
}
void f(unsigned val, int bit) {
f(val, bit, bit);
}
void sf(int64_t val, int msb, int lsb) {
int nbits = msb - lsb + 1;
int64_t chk = val >> (nbits - 1);
guarantee (chk == -1 || chk == 0, "Field too big for insn");
unsigned uval = val;
unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
uval &= mask;
f(uval, lsb + nbits - 1, lsb);
}
void rf(Register r, int lsb) {
f(r->encoding_nocheck(), lsb + 4, lsb);
}
// reg|ZR
void zrf(Register r, int lsb) {
f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
}
// reg|SP
void srf(Register r, int lsb) {
f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
}
void rf(FloatRegister r, int lsb) {
f(r->encoding_nocheck(), lsb + 4, lsb);
}
void prf(PRegister r, int lsb) {
f(r->encoding_nocheck(), lsb + 3, lsb);
}
void pgrf(PRegister r, int lsb) {
f(r->encoding_nocheck(), lsb + 2, lsb);
}
unsigned get(int msb = 31, int lsb = 0) {
int nbits = msb - lsb + 1;
unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)) << lsb;
assert_cond((bits & mask) == mask);
return (insn & mask) >> lsb;
}
void fixed(unsigned value, unsigned mask) {
assert_cond ((mask & bits) == 0);
#ifdef ASSERT
bits |= mask;
#endif
insn |= value;
}
};
#define starti Instruction_aarch64 current_insn(this);
class PrePost {
int _offset;
Register _r;
public:
PrePost(Register reg, int o) : _offset(o), _r(reg) { }
int offset() { return _offset; }
Register reg() { return _r; }
};
class Pre : public PrePost {
public:
Pre(Register reg, int o) : PrePost(reg, o) { }
};
class Post : public PrePost {
Register _idx;
bool _is_postreg;
public:
Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
Register idx_reg() { return _idx; }
bool is_postreg() {return _is_postreg; }
};
namespace ext
{
enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
};
// Addressing modes
class Address {
public:
enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
base_plus_offset_reg, literal };
// Shift and extend for base reg + reg offset addressing
class extend {
int _option, _shift;
ext::operation _op;
public:
extend() { }
extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
int option() const{ return _option; }
int shift() const { return _shift; }
ext::operation op() const { return _op; }
};
class uxtw : public extend {
public:
uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
};
class lsl : public extend {
public:
lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
};
class sxtw : public extend {
public:
sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
};
class sxtx : public extend {
public:
sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
};
private:
Register _base;
Register _index;
int64_t _offset;
enum mode _mode;
extend _ext;
RelocationHolder _rspec;
// Typically we use AddressLiterals we want to use their rval
// However in some situations we want the lval (effect address) of
// the item. We provide a special factory for making those lvals.
bool _is_lval;
// If the target is far we'll need to load the ea of this to a
// register to reach it. Otherwise if near we can do PC-relative
// addressing.
address _target;
public:
Address()
: _mode(no_mode) { }
Address(Register r)
: _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
template<typename T, ENABLE_IF(std::is_integral<T>::value)>
Address(Register r, T o)
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) {}
Address(Register r, ByteSize disp)
: Address(r, in_bytes(disp)) { }
Address(Register r, Register r1, extend ext = lsl())
: _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
_ext(ext), _target(0) { }
Address(Pre p)
: _base(p.reg()), _offset(p.offset()), _mode(pre) { }
Address(Post p)
: _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()),
_mode(p.is_postreg() ? post_reg : post), _target(0) { }
Address(address target, RelocationHolder const& rspec)
: _mode(literal),
_rspec(rspec),
_is_lval(false),
_target(target) { }
Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
Address(Register base, RegisterOrConstant index, extend ext = lsl())
: _base (base),
_offset(0), _ext(ext), _target(0) {
if (index.is_register()) {
_mode = base_plus_offset_reg;
_index = index.as_register();
} else {
guarantee(ext.option() == ext::uxtx, "should be");
assert(index.is_constant(), "should be");
_mode = base_plus_offset;
_offset = index.as_constant() << ext.shift();
}
}
Register base() const {
guarantee((_mode == base_plus_offset || _mode == base_plus_offset_reg
|| _mode == post || _mode == post_reg),
"wrong mode");
return _base;
}
int64_t offset() const {
return _offset;
}
Register index() const {
return _index;
}
mode getMode() const {
return _mode;
}
bool uses(Register reg) const { return _base == reg || _index == reg; }
address target() const { return _target; }
const RelocationHolder& rspec() const { return _rspec; }
void encode(Instruction_aarch64 *i) const {
i->f(0b111, 29, 27);
i->srf(_base, 5);
switch(_mode) {
case base_plus_offset:
{
unsigned size = i->get(31, 30);
if (i->get(26, 26) && i->get(23, 23)) {
// SIMD Q Type - Size = 128 bits
assert(size == 0, "bad size");
size = 0b100;
}
assert(offset_ok_for_immed(_offset, size),
"must be, was: " INT64_FORMAT ", %d", _offset, size);
unsigned mask = (1 << size) - 1;
if (_offset < 0 || _offset & mask) {
i->f(0b00, 25, 24);
i->f(0, 21), i->f(0b00, 11, 10);
i->sf(_offset, 20, 12);
} else {
i->f(0b01, 25, 24);
i->f(_offset >> size, 21, 10);
}
}
break;
case base_plus_offset_reg:
{
i->f(0b00, 25, 24);
i->f(1, 21);
i->rf(_index, 16);
i->f(_ext.option(), 15, 13);
unsigned size = i->get(31, 30);
if (i->get(26, 26) && i->get(23, 23)) {
// SIMD Q Type - Size = 128 bits
assert(size == 0, "bad size");
size = 0b100;
}
if (size == 0) // It's a byte
i->f(_ext.shift() >= 0, 12);
else {
assert(_ext.shift() <= 0 || _ext.shift() == (int)size, "bad shift");
i->f(_ext.shift() > 0, 12);
}
i->f(0b10, 11, 10);
}
break;
case pre:
i->f(0b00, 25, 24);
i->f(0, 21), i->f(0b11, 11, 10);
i->sf(_offset, 20, 12);
break;
case post:
i->f(0b00, 25, 24);
i->f(0, 21), i->f(0b01, 11, 10);
i->sf(_offset, 20, 12);
break;
default:
ShouldNotReachHere();
}
}
void encode_pair(Instruction_aarch64 *i) const {
switch(_mode) {
case base_plus_offset:
i->f(0b010, 25, 23);
break;
case pre:
i->f(0b011, 25, 23);
break;
case post:
i->f(0b001, 25, 23);
break;
default:
ShouldNotReachHere();
}
unsigned size; // Operand shift in 32-bit words
if (i->get(26, 26)) { // float
switch(i->get(31, 30)) {
case 0b10:
size = 2; break;
case 0b01:
size = 1; break;
case 0b00:
size = 0; break;
default:
ShouldNotReachHere();
size = 0; // unreachable
}
} else {
size = i->get(31, 31);
}
size = 4 << size;
guarantee(_offset % size == 0, "bad offset");
i->sf(_offset / size, 21, 15);
i->srf(_base, 5);
}
void encode_nontemporal_pair(Instruction_aarch64 *i) const {
// Only base + offset is allowed
i->f(0b000, 25, 23);
unsigned size = i->get(31, 31);
size = 4 << size;
guarantee(_offset % size == 0, "bad offset");
i->sf(_offset / size, 21, 15);
i->srf(_base, 5);
guarantee(_mode == Address::base_plus_offset,
"Bad addressing mode for non-temporal op");
}
void lea(MacroAssembler *, Register) const;
static bool offset_ok_for_immed(int64_t offset, uint shift);
static bool offset_ok_for_sve_immed(int64_t offset, int shift, int vl /* sve vector length */) {
if (offset % vl == 0) {
// Convert address offset into sve imm offset (MUL VL).
int sve_offset = offset / vl;
if (((-(1 << (shift - 1))) <= sve_offset) && (sve_offset < (1 << (shift - 1)))) {
// sve_offset can be encoded
return true;
}
}
return false;
}
};
// Convience classes
class RuntimeAddress: public Address {
public:
RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
};
class OopAddress: public Address {
public:
OopAddress(address target) : Address(target, relocInfo::oop_type){}
};
class ExternalAddress: public Address {
private:
static relocInfo::relocType reloc_for_target(address target) {
// Sometimes ExternalAddress is used for values which aren't
// exactly addresses, like the card table base.
// external_word_type can't be used for values in the first page
// so just skip the reloc in that case.
return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
}
public:
ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
};
class InternalAddress: public Address {
public:
InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
};
const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers *
FloatRegisterImpl::save_slots_per_register;
typedef enum {
PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
} prfop;
class Assembler : public AbstractAssembler {
public:
#ifndef PRODUCT
static const uintptr_t asm_bp;
void emit_int32(jint x) {
if ((uintptr_t)pc() == asm_bp)
NOP();
AbstractAssembler::emit_int32(x);
}
#else
void emit_int32(jint x) {
AbstractAssembler::emit_int32(x);
}
#endif
enum { instruction_size = 4 };
//---< calculate length of instruction >---
// We just use the values set above.
// instruction must start at passed address
static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
//---< longest instructions >---
static unsigned int instr_maxlen() { return instruction_size; }
Address adjust(Register base, int offset, bool preIncrement) {
if (preIncrement)
return Address(Pre(base, offset));
else
return Address(Post(base, offset));
}
Address pre(Register base, int offset) {
return adjust(base, offset, true);
}
Address post(Register base, int offset) {
return adjust(base, offset, false);
}
Address post(Register base, Register idx) {
return Address(Post(base, idx));
}
static address locate_next_instruction(address inst);
#define f current_insn.f
#define sf current_insn.sf
#define rf current_insn.rf
#define srf current_insn.srf
#define zrf current_insn.zrf
#define prf current_insn.prf
#define pgrf current_insn.pgrf
#define fixed current_insn.fixed
typedef void (Assembler::* uncond_branch_insn)(address dest);
typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
typedef void (Assembler::* prefetch_insn)(address target, prfop);
void wrap_label(Label &L, uncond_branch_insn insn);
void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
void wrap_label(Label &L, prfop, prefetch_insn insn);
// PC-rel. addressing
void adr(Register Rd, address dest);
void _adrp(Register Rd, address dest);
void adr(Register Rd, const Address &dest);
void _adrp(Register Rd, const Address &dest);
void adr(Register Rd, Label &L) {
wrap_label(Rd, L, &Assembler::Assembler::adr);
}
void _adrp(Register Rd, Label &L) {
wrap_label(Rd, L, &Assembler::_adrp);
}
void adrp(Register Rd, const Address &dest, uint64_t &offset);
#undef INSN
void add_sub_immediate(Instruction_aarch64 ¤t_insn, Register Rd, Register Rn,
unsigned uimm, int op, int negated_op);
// Add/subtract (immediate)
#define INSN(NAME, decode, negated) \
void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
starti; \
f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
zrf(Rd, 0), srf(Rn, 5); \
} \
\
void NAME(Register Rd, Register Rn, unsigned imm) { \
starti; \
add_sub_immediate(current_insn, Rd, Rn, imm, decode, negated); \
}
INSN(addsw, 0b001, 0b011);
INSN(subsw, 0b011, 0b001);
INSN(adds, 0b101, 0b111);
INSN(subs, 0b111, 0b101);
#undef INSN
#define INSN(NAME, decode, negated) \
void NAME(Register Rd, Register Rn, unsigned imm) { \
starti; \
add_sub_immediate(current_insn, Rd, Rn, imm, decode, negated); \
}
INSN(addw, 0b000, 0b010);
INSN(subw, 0b010, 0b000);
INSN(add, 0b100, 0b110);
INSN(sub, 0b110, 0b100);
#undef INSN
// Logical (immediate)
#define INSN(NAME, decode, is32) \
void NAME(Register Rd, Register Rn, uint64_t imm) { \
starti; \
uint32_t val = encode_logical_immediate(is32, imm); \
f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
srf(Rd, 0), zrf(Rn, 5); \
}
INSN(andw, 0b000, true);
INSN(orrw, 0b001, true);
INSN(eorw, 0b010, true);
INSN(andr, 0b100, false);
INSN(orr, 0b101, false);
INSN(eor, 0b110, false);
#undef INSN
#define INSN(NAME, decode, is32) \
void NAME(Register Rd, Register Rn, uint64_t imm) { \
starti; \
uint32_t val = encode_logical_immediate(is32, imm); \
f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
zrf(Rd, 0), zrf(Rn, 5); \
}
INSN(ands, 0b111, false);
INSN(andsw, 0b011, true);
#undef INSN
// Move wide (immediate)
#define INSN(NAME, opcode) \
void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
assert_cond((shift/16)*16 == shift); \
starti; \
f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
f(imm, 20, 5); \
rf(Rd, 0); \
}
INSN(movnw, 0b000);
INSN(movzw, 0b010);
INSN(movkw, 0b011);
INSN(movn, 0b100);
INSN(movz, 0b110);
INSN(movk, 0b111);
#undef INSN
// Bitfield
#define INSN(NAME, opcode, size) \
void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
starti; \
guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
zrf(Rn, 5), rf(Rd, 0); \
}
INSN(sbfmw, 0b0001001100, 0);
INSN(bfmw, 0b0011001100, 0);
INSN(ubfmw, 0b0101001100, 0);
INSN(sbfm, 0b1001001101, 1);
INSN(bfm, 0b1011001101, 1);
INSN(ubfm, 0b1101001101, 1);
#undef INSN
// Extract
#define INSN(NAME, opcode, size) \
void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
starti; \
guarantee(size == 1 || imms < 32, "incorrect imms"); \
f(opcode, 31, 21), f(imms, 15, 10); \
zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
}
INSN(extrw, 0b00010011100, 0);
INSN(extr, 0b10010011110, 1);
#undef INSN
// The maximum range of a branch is fixed for the AArch64
// architecture. In debug mode we shrink it in order to test
// trampolines, but not so small that branches in the interpreter
// are out of range.
static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
static bool reachable_from_branch_at(address branch, address target) {
return uabs(target - branch) < branch_range;
}
// Unconditional branch (immediate)
#define INSN(NAME, opcode) \
void NAME(address dest) { \
starti; \
int64_t offset = (dest - pc()) >> 2; \
DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
} \
void NAME(Label &L) { \
wrap_label(L, &Assembler::NAME); \
} \
void NAME(const Address &dest);
INSN(b, 0);
INSN(bl, 1);
#undef INSN
// Compare & branch (immediate)
#define INSN(NAME, opcode) \
void NAME(Register Rt, address dest) { \
int64_t offset = (dest - pc()) >> 2; \
starti; \
f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
} \
void NAME(Register Rt, Label &L) { \
wrap_label(Rt, L, &Assembler::NAME); \
}
INSN(cbzw, 0b00110100);
INSN(cbnzw, 0b00110101);
INSN(cbz, 0b10110100);
INSN(cbnz, 0b10110101);
#undef INSN
// Test & branch (immediate)
#define INSN(NAME, opcode) \
void NAME(Register Rt, int bitpos, address dest) { \
int64_t offset = (dest - pc()) >> 2; \
int b5 = bitpos >> 5; \
bitpos &= 0x1f; \
starti; \
f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
rf(Rt, 0); \
} \
void NAME(Register Rt, int bitpos, Label &L) { \
wrap_label(Rt, bitpos, L, &Assembler::NAME); \
}
INSN(tbz, 0b0110110);
INSN(tbnz, 0b0110111);
#undef INSN
// Conditional branch (immediate)
enum Condition
{EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
void br(Condition cond, address dest) {
int64_t offset = (dest - pc()) >> 2;
starti;
f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
}
#define INSN(NAME, cond) \
void NAME(address dest) { \
br(cond, dest); \
}
INSN(beq, EQ);
INSN(bne, NE);
INSN(bhs, HS);
INSN(bcs, CS);
INSN(blo, LO);
INSN(bcc, CC);
INSN(bmi, MI);
INSN(bpl, PL);
INSN(bvs, VS);
INSN(bvc, VC);
INSN(bhi, HI);
INSN(bls, LS);
INSN(bge, GE);
INSN(blt, LT);
INSN(bgt, GT);
INSN(ble, LE);
INSN(bal, AL);
INSN(bnv, NV);
void br(Condition cc, Label &L);
#undef INSN
// Exception generation
void generate_exception(int opc, int op2, int LL, unsigned imm) {
starti;
f(0b11010100, 31, 24);
f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
}
#define INSN(NAME, opc, op2, LL) \
void NAME(unsigned imm) { \
generate_exception(opc, op2, LL, imm); \
}
INSN(svc, 0b000, 0, 0b01);
INSN(hvc, 0b000, 0, 0b10);
INSN(smc, 0b000, 0, 0b11);
INSN(brk, 0b001, 0, 0b00);
INSN(hlt, 0b010, 0, 0b00);
INSN(dcps1, 0b101, 0, 0b01);
INSN(dcps2, 0b101, 0, 0b10);
INSN(dcps3, 0b101, 0, 0b11);
#undef INSN
// System
void system(int op0, int op1, int CRn, int CRm, int op2,
Register rt = dummy_reg)
{
starti;
f(0b11010101000, 31, 21);
f(op0, 20, 19);
f(op1, 18, 16);
f(CRn, 15, 12);
f(CRm, 11, 8);
f(op2, 7, 5);
rf(rt, 0);
}
// Hint instructions
#define INSN(NAME, crm, op2) \
void NAME() { \
system(0b00, 0b011, 0b0010, crm, op2); \
}
INSN(nop, 0b000, 0b0000);
INSN(yield, 0b000, 0b0001);
INSN(wfe, 0b000, 0b0010);
INSN(wfi, 0b000, 0b0011);