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@accelr-net

ACCELR

Acceleration done right

Popular repositories

  1. udma_uart_vip udma_uart_vip Public

    VIP and simulation scripts for PULP's UDMA UART module

    SystemVerilog 7 1

  2. alveo-memory-tester alveo-memory-tester Public

    Memory read write tester for Xilinx Alveo cards

    SystemVerilog 1 1

  3. tvm-riscv-demo tvm-riscv-demo Public

    Demonstrator on running TVM on RISC-V with RN18 and KWS examples

    Python 1

  4. tf2trt_conversion tf2trt_conversion Public

    Helper code and example code to convert a TensorFlow 2 classifier model (RN50-V1) to Nvidia's TensorRT

    Python

  5. kws-tvm kws-tvm Public

    Convert a KWS network from pytorch to TVM and measure perofrmance

    Python

  6. axis_fifo_unit_test axis_fifo_unit_test Public

    Unit test for AXIS FIFO that uses the Xilinx AXI4 stream VIP

    Verilog

Repositories

Showing 6 of 6 repositories
  • udma_uart_vip Public

    VIP and simulation scripts for PULP's UDMA UART module

    SystemVerilog 7 Apache-2.0 1 0 0 Updated Apr 30, 2024
  • tvm-riscv-demo Public

    Demonstrator on running TVM on RISC-V with RN18 and KWS examples

    Python 1 MIT 0 0 0 Updated Jan 21, 2024
  • axis_fifo_unit_test Public

    Unit test for AXIS FIFO that uses the Xilinx AXI4 stream VIP

    Verilog 0 Apache-2.0 0 0 0 Updated Dec 4, 2023
  • tf2trt_conversion Public

    Helper code and example code to convert a TensorFlow 2 classifier model (RN50-V1) to Nvidia's TensorRT

    Python 0 0 0 0 Updated Aug 9, 2023
  • kws-tvm Public

    Convert a KWS network from pytorch to TVM and measure perofrmance

    Python 0 0 0 0 Updated Aug 8, 2023
  • alveo-memory-tester Public

    Memory read write tester for Xilinx Alveo cards

    SystemVerilog 1 1 0 0 Updated Aug 8, 2023

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