Artifacts for refs/heads/main at ce06fc4

adafruit · Nov 20, 2021 · 5bff1d5 · 5bff1d5
2 parents d00e13d + ce06fc4
commit 5bff1d5
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Showing 7 changed files with 75 additions and 34 deletions.
diff --git a/broadcom/gen/bcm2711_lpa.h b/broadcom/gen/bcm2711_lpa.h
@@ -18,8 +18,8 @@
  * @file     broadcom/gen//bcm2711_lpa.h
  * @brief    CMSIS HeaderFile
  * @version  A
- * @date     19. November 2021
- * @note     Generated by SVDConv V3.3.35 on Friday, 19.11.2021 19:26:14
+ * @date     20. November 2021
+ * @note     Generated by SVDConv V3.3.35 on Saturday, 20.11.2021 01:03:40
  *           from File 'svd/gen/bcm2711_lpa.svd',
  */
 
@@ -5685,8 +5685,8 @@ typedef struct {                                /*!< (@ 0xFE215040) UART1 Struct
 
     struct {
       __IOM uint32_t nPENDING   : 1;            /*!< [0..0] No pending interrupt                                               */
-      __IOM uint32_t TX_READY   : 1;            /*!< [1..1] Transmit FIFO is empty                                             */
-      __IOM uint32_t DATA_READY : 1;            /*!< [2..2] Receive FIFO has at least 1 byte                                   */
+      __IOM uint32_t DATA_READY : 1;            /*!< [1..1] Receive FIFO has at least 1 byte                                   */
+      __IOM uint32_t TX_READY   : 1;            /*!< [2..2] Transmit FIFO is empty                                             */
             uint32_t            : 29;
     } IIR_b;
   } ;
@@ -14766,10 +14766,10 @@ typedef struct {                                /*!< (@ 0xFE300000) EMMC Structu
 #define UART1_IER_DATA_READY_Msk          (0x1UL)                   /*!< DATA_READY (Bitfield-Mask: 0x01)                      */
 /* =========================================================  BAUDH  ========================================================= */
 /* ==========================================================  IIR  ========================================================== */
-#define UART1_IIR_DATA_READY_Pos          (2UL)                     /*!< DATA_READY (Bit 2)                                    */
-#define UART1_IIR_DATA_READY_Msk          (0x4UL)                   /*!< DATA_READY (Bitfield-Mask: 0x01)                      */
-#define UART1_IIR_TX_READY_Pos            (1UL)                     /*!< TX_READY (Bit 1)                                      */
-#define UART1_IIR_TX_READY_Msk            (0x2UL)                   /*!< TX_READY (Bitfield-Mask: 0x01)                        */
+#define UART1_IIR_TX_READY_Pos            (2UL)                     /*!< TX_READY (Bit 2)                                      */
+#define UART1_IIR_TX_READY_Msk            (0x4UL)                   /*!< TX_READY (Bitfield-Mask: 0x01)                        */
+#define UART1_IIR_DATA_READY_Pos          (1UL)                     /*!< DATA_READY (Bit 1)                                    */
+#define UART1_IIR_DATA_READY_Msk          (0x2UL)                   /*!< DATA_READY (Bitfield-Mask: 0x01)                      */
 #define UART1_IIR_nPENDING_Pos            (0UL)                     /*!< nPENDING (Bit 0)                                      */
 #define UART1_IIR_nPENDING_Msk            (0x1UL)                   /*!< nPENDING (Bitfield-Mask: 0x01)                        */
 /* ==========================================================  LCR  ========================================================== */

diff --git a/broadcom/gen/bcm2837_lpa.h b/broadcom/gen/bcm2837_lpa.h
@@ -18,8 +18,8 @@
  * @file     broadcom/gen//bcm2837_lpa.h
  * @brief    CMSIS HeaderFile
  * @version  A
- * @date     19. November 2021
- * @note     Generated by SVDConv V3.3.35 on Friday, 19.11.2021 19:26:14
+ * @date     20. November 2021
+ * @note     Generated by SVDConv V3.3.35 on Saturday, 20.11.2021 01:03:40
  *           from File 'svd/gen/bcm2837_lpa.svd',
  */
 
@@ -1920,8 +1920,8 @@ typedef struct {                                /*!< (@ 0x3F215040) UART1 Struct
 
     struct {
       __IOM uint32_t nPENDING   : 1;            /*!< [0..0] No pending interrupt                                               */
-      __IOM uint32_t TX_READY   : 1;            /*!< [1..1] Transmit FIFO is empty                                             */
-      __IOM uint32_t DATA_READY : 1;            /*!< [2..2] Receive FIFO has at least 1 byte                                   */
+      __IOM uint32_t DATA_READY : 1;            /*!< [1..1] Receive FIFO has at least 1 byte                                   */
+      __IOM uint32_t TX_READY   : 1;            /*!< [2..2] Transmit FIFO is empty                                             */
             uint32_t            : 29;
     } IIR_b;
   } ;
@@ -5693,10 +5693,10 @@ typedef struct {                                /*!< (@ 0x3F300000) EMMC Structu
 #define UART1_IER_DATA_READY_Msk          (0x1UL)                   /*!< DATA_READY (Bitfield-Mask: 0x01)                      */
 /* =========================================================  BAUDH  ========================================================= */
 /* ==========================================================  IIR  ========================================================== */
-#define UART1_IIR_DATA_READY_Pos          (2UL)                     /*!< DATA_READY (Bit 2)                                    */
-#define UART1_IIR_DATA_READY_Msk          (0x4UL)                   /*!< DATA_READY (Bitfield-Mask: 0x01)                      */
-#define UART1_IIR_TX_READY_Pos            (1UL)                     /*!< TX_READY (Bit 1)                                      */
-#define UART1_IIR_TX_READY_Msk            (0x2UL)                   /*!< TX_READY (Bitfield-Mask: 0x01)                        */
+#define UART1_IIR_TX_READY_Pos            (2UL)                     /*!< TX_READY (Bit 2)                                      */
+#define UART1_IIR_TX_READY_Msk            (0x4UL)                   /*!< TX_READY (Bitfield-Mask: 0x01)                        */
+#define UART1_IIR_DATA_READY_Pos          (1UL)                     /*!< DATA_READY (Bit 1)                                    */
+#define UART1_IIR_DATA_READY_Msk          (0x2UL)                   /*!< DATA_READY (Bitfield-Mask: 0x01)                      */
 #define UART1_IIR_nPENDING_Pos            (0UL)                     /*!< nPENDING (Bit 0)                                      */
 #define UART1_IIR_nPENDING_Msk            (0x1UL)                   /*!< nPENDING (Bitfield-Mask: 0x01)                        */
 /* ==========================================================  LCR  ========================================================== */

diff --git a/broadcom/interrupts.c b/broadcom/interrupts.c
@@ -34,15 +34,18 @@ void BP_EnableIRQs(void) {
     _current_interrupt = INTERRUPT_COUNT;
     #endif
     __asm__("msr    daifclr, #2");
+    __asm__("isb");
 }
 
 void BP_DisableIRQs(void) {
     __asm__("msr    daifset, #2");
+    __asm__("isb");
 }
 
 __attribute__((weak)) void handle_irq(void) {
     #if BCM_VERSION != 2711
     static const uint8_t basic_to_id[] = {7, 9, 10, 18, 19, 53, 54, 55, 56, 57, 62};
+    __asm__("dsb sy");
     while (LIC->BASIC_PENDING != 0) {
         uint32_t current_pending = LIC->BASIC_PENDING;
         // We don't allow for nested interrupts so look through the pending bits in
@@ -100,35 +103,43 @@ __attribute__((weak)) void handle_irq(void) {
             while(true) {}
         }
         _current_interrupt = interrupt_id;
+        // Put aggressive data access barriers around the interrupt handler
+        __asm__ volatile("dsb sy" : : : "memory");
         handler();
+        __asm__ volatile("dsb sy" : : : "memory");
         _current_interrupt = INTERRUPT_COUNT;
     }
     #else
+
+    __asm__ volatile("dsb sy" : : : "memory");
     while (GIC_CPU->GICC_HPPIR_b.INTERRUPT_ID < INTERRUPT_COUNT) {
         // This register changes state after being read so make sure to read it
         // all at once. We need the full value to pass back to EOIR later.
         uint32_t current_interrupt = GIC_CPU->GICC_IAR;
 
-        // Turn on interrupts to allow for preemption.
-        BP_EnableIRQs();
-
         uint32_t interrupt_id = current_interrupt & GIC_CPU_GICC_IAR_INTERRUPT_ID_Msk;
         if (interrupt_id >= INTERRUPT_COUNT) {
             break;
         }
 
+        // Turn on interrupts to allow for preemption.
+        BP_EnableIRQs();
+
         void(* handler)(void) = interrupt_handlers[interrupt_id];
         if (handler == NULL) {
             // Unhandled interrupt. Read interrupt_id from GDB to find out the mistake.
             while(true) {}
         }
+        __asm__ volatile("dsb sy" : : : "memory");
         handler();
+        __asm__ volatile("dsb sy" : : : "memory");
 
         // Turn off interrupts while we do housekeeping.
         BP_DisableIRQs();
 
         GIC_CPU->GICC_EOIR = current_interrupt;
     }
+    __asm__ volatile("dsb sy" : : : "memory");
     #endif
 }
 
@@ -141,6 +152,7 @@ void BP_SetMinPriority(uint8_t priority) {
 
 // We mimic the NVIC used in Cortex M SoCs.
 void BP_EnableIRQ(IRQn_Type IRQn) {
+    __asm__("dsb sy");
     #if BCM_VERSION != 2711
     if (IRQn < 32) {
         LIC->ENABLE_1 = 1 << IRQn;
@@ -155,9 +167,11 @@ void BP_EnableIRQ(IRQn_Type IRQn) {
     volatile uint32_t* enabled = (volatile uint32_t*) &GIC_DIST->GICD_ISENABLER;
     enabled[IRQn / 32] = 1 << (IRQn % 32);
     #endif
+    __asm__("dsb sy");
 }
 
 bool BP_GetEnableIRQ(IRQn_Type IRQn) {
+    __asm__("dsb sy");
     #if BCM_VERSION != 2711
     if (IRQn < 32) {
         return (LIC->ENABLE_1 & (1 << IRQn)) != 0;
@@ -170,9 +184,11 @@ bool BP_GetEnableIRQ(IRQn_Type IRQn) {
     volatile uint8_t* targets = (volatile uint8_t*) &GIC_DIST->GICD_ITARGETSR;
     return (targets[IRQn] & (1 << CPU_Index())) != 0;
     #endif
+    __asm__("dsb sy");
 }
 
 void BP_DisableIRQ(IRQn_Type IRQn) {
+    __asm__("dsb sy");
     #if BCM_VERSION != 2711
     if (IRQn < 32) {
         LIC->DISABLE_1 = 1 << IRQn;
@@ -185,9 +201,11 @@ void BP_DisableIRQ(IRQn_Type IRQn) {
     volatile uint8_t* targets = (volatile uint8_t*) &GIC_DIST->GICD_ITARGETSR;
     targets[IRQn] &= ~(1 << CPU_Index());
     #endif
+    __asm__("dsb sy");
 }
 
 bool BP_GetPendingIRQ(IRQn_Type IRQn) {
+    __asm__("dsb sy");
     #if BCM_VERSION == 2711
     volatile uint32_t* pending = (volatile uint32_t*) &GIC_DIST->GICD_ISPENDR;
     return (pending[IRQn / 32] & (1 << (IRQn % 32))) != 0;
@@ -200,29 +218,36 @@ bool BP_GetPendingIRQ(IRQn_Type IRQn) {
         return (LIC->BASIC_PENDING & (1 << (IRQn - 64))) != 0;
     }
     #endif
+    __asm__("dsb sy");
 }
 
 void BP_SetPendingIRQ(IRQn_Type IRQn) {
     #if BCM_VERSION == 2711
+    __asm__("dsb sy");
     volatile uint32_t* set_pending = (volatile uint32_t*) &GIC_DIST->GICD_ISPENDR;
     set_pending[IRQn / 32] = 1 << (IRQn % 32);
+    __asm__("dsb sy");
     #endif
     // The legacy interrupt controller cannot set interrupts pending. The interrupt
     // state is directly tied to the source peripheral.
 }
 
 void BP_ClearPendingIRQ(IRQn_Type IRQn)  {
     #if BCM_VERSION == 2711
+    __asm__("dsb sy");
     volatile uint32_t* clear_pending = (volatile uint32_t*) &GIC_DIST->GICD_ICPENDR;
     clear_pending[IRQn / 32] = 1 << (IRQn % 32);
+    __asm__("dsb sy");
     #endif
     // The legacy interrupt controller cannot clear interrupts. They must be done
     // on the peripheral.
 }
 
 bool BP_GetActive(IRQn_Type IRQn) {
     #if BCM_VERSION == 2711
+    __asm__("dsb sy");
     volatile uint32_t* active = (volatile uint32_t*) &GIC_DIST->GICD_ISACTIVER;
+    __asm__("dsb sy");
     return (active[IRQn / 32] & (1 << (IRQn % 32))) != 0;
     #else
     return _current_interrupt == IRQn;
@@ -231,8 +256,10 @@ bool BP_GetActive(IRQn_Type IRQn) {
 
 void BP_SetPriority(IRQn_Type IRQn, uint8_t priority) {
     #if BCM_VERSION == 2711
+    __asm__("dsb sy");
     volatile uint8_t* irq_priority = (volatile uint8_t*) &GIC_DIST->GICD_IPRIORITYR;
     irq_priority[IRQn] = priority;
+    __asm__("dsb sy");
     #else
     (void) IRQn;
     (void) priority;

diff --git a/broadcom/vcmailbox.c b/broadcom/vcmailbox.c
@@ -5,18 +5,27 @@
 #include "broadcom/defines.h"
 #include "broadcom/gen/vcmailbox.h"
 
-
 __attribute__((target("strict-align"))) bool vcmailbox_request(volatile vcmailbox_buffer_t* buffer) {
     size_t buffer_size = buffer->buffer_size;
     buffer->code = VCMAILBOX_CODE_PROCESS_REQUEST;
     while (VCMAILBOX->STATUS0_b.FULL) {}
+    while (!VCMAILBOX->STATUS0_b.EMPTY) {
+        VCMAILBOX->READ;
+    }
     #pragma GCC diagnostic push
     #pragma GCC diagnostic ignored "-Wpointer-to-int-cast"
     uint32_t buffer_address = 0x00000000 | (uint32_t) buffer | 8;
     #pragma GCC diagnostic pop
     data_clean(buffer, buffer_size);
+    __asm__("dsb sy");
     VCMAILBOX->WRITE = buffer_address;
-    while (VCMAILBOX->STATUS0_b.EMPTY || VCMAILBOX->READ != buffer_address) {}
+    size_t count = 0;
+    while (VCMAILBOX->STATUS0_b.EMPTY || VCMAILBOX->READ != buffer_address) {
+        count++;
+        if (count > 10000000) {
+            return false;
+        }
+    }
     data_invalidate(buffer, buffer_size);
     return buffer->code == VCMAILBOX_CODE_REQUEST_SUCCESSFUL;
 }
@@ -181,7 +190,9 @@ uint32_t vcmailbox_get_temperature(void) {
     vcmailbox_get_temperature_t* tag = (vcmailbox_get_temperature_t*) &buf->data;
     *tag = VCMAILBOX_GET_TEMPERATURE_DEFAULTS;
     tag->request.temperature_id = 0; // always 0
-    vcmailbox_request(buf);
+    if (!vcmailbox_request(buf)) {
+        return 0;
+    }
     return tag->response.value;
 }
 

diff --git a/svd/gen/bcm2711_lpa.svd b/svd/gen/bcm2711_lpa.svd
@@ -10652,15 +10652,16 @@
                   <access>read-write</access>
                   <resetValue>0x0000b001</resetValue>
                   <fields>
+                        <!-- These bits are incorrect in the datasheets. -->
                         <field>
-                            <name>DATA_READY</name>
-                            <description>Receive FIFO has at least 1 byte</description>
+                            <name>TX_READY</name>
+                            <description>Transmit FIFO is empty</description>
                             <bitOffset>2</bitOffset>
                             <bitWidth>1</bitWidth>
                         </field>
                         <field>
-                            <name>TX_READY</name>
-                            <description>Transmit FIFO is empty</description>
+                            <name>DATA_READY</name>
+                            <description>Receive FIFO has at least 1 byte</description>
                             <bitOffset>1</bitOffset>
                             <bitWidth>1</bitWidth>
                         </field>

diff --git a/svd/gen/bcm2837_lpa.svd b/svd/gen/bcm2837_lpa.svd
@@ -10607,15 +10607,16 @@
                   <access>read-write</access>
                   <resetValue>0x0000b001</resetValue>
                   <fields>
+                        <!-- These bits are incorrect in the datasheets. -->
                         <field>
-                            <name>DATA_READY</name>
-                            <description>Receive FIFO has at least 1 byte</description>
+                            <name>TX_READY</name>
+                            <description>Transmit FIFO is empty</description>
                             <bitOffset>2</bitOffset>
                             <bitWidth>1</bitWidth>
                         </field>
                         <field>
-                            <name>TX_READY</name>
-                            <description>Transmit FIFO is empty</description>
+                            <name>DATA_READY</name>
+                            <description>Receive FIFO has at least 1 byte</description>
                             <bitOffset>1</bitOffset>
                             <bitWidth>1</bitWidth>
                         </field>

diff --git a/svd/peripherals/bcm_aux.svd.jinja b/svd/peripherals/bcm_aux.svd.jinja
@@ -147,15 +147,16 @@
                   <access>read-write</access>
                   <resetValue>0x0000b001</resetValue>
                   <fields>
+                        <!-- These bits are incorrect in the datasheets. -->
                         <field>
-                            <name>DATA_READY</name>
-                            <description>Receive FIFO has at least 1 byte</description>
+                            <name>TX_READY</name>
+                            <description>Transmit FIFO is empty</description>
                             <bitOffset>2</bitOffset>
                             <bitWidth>1</bitWidth>
                         </field>
                         <field>
-                            <name>TX_READY</name>
-                            <description>Transmit FIFO is empty</description>
+                            <name>DATA_READY</name>
+                            <description>Receive FIFO has at least 1 byte</description>
                             <bitOffset>1</bitOffset>
                             <bitWidth>1</bitWidth>
                         </field>