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ZUMA

Introduction

This repository contains the ZUMA FPGA overlay architecture system that was introduced by Brant and Lemieux in 2012 and later extended by Wiersema, Bockhorn, Platzner, and several students of Paderborn University.

The folders contain a number of components needed to use ZUMA, as well as examples and tests.

Directory structure

doc/ Contains the user's manual.
example/ Contains example files to get started.
external/ Required third party tools as GIT submodules.
source/ Scripts to generate the ZUMA Verilog components and bitstreams.
tests/ Included scripts used to test ZUMA components.
tests/integration/ Python unit tests for the ZUMA scripts.
verilog/ Verilog project files to instantiate a ZUMA system.
license.txt The license under which ZUMA can be used.
Makefile Global Makefile to prepare a working tool flow.
toolpaths.py Global path setup.

Building

You will need a Linux installation with a working Python 2.7 installation. You will also need the python libraries plumbum and numpy and optional graphviz when you want to plot some internal graphs. Then just run make from the root directory.

For more details see the user's manual, Section 2.

Running the Tools

Calling the Python script compile.sh test.v will automatically build the ZUMA system Verilog ZUMA_custom_generated.v, and a bitstream hex file output.hex, which can be used to synthesize and configure a ZUMA system. By passing other circuit files, modifying the example ZUMA configuration file zuma_config.py, or providing an alternative configuration file via the --config command line switch, custom architectures and bitstreams can be generated.

For more details see the user's manual, Section 3.

Including a ZUMA Overlay in a Project

Once the Verilog architecture is created, and a hex bitstream is generated, the ZUMA system can be compiled and used. The generated Verilog file that describes the virtual fabric, along with the files in the verilog/generic/ and verilog/platform/(platform)/ directories should be included in a new Xilinx / Altera project, although getting it to work for Altera devices might require some (read: significant amount of) additional work.

For more details see the user's manual, Section 5.

License

See the license file for details.

List of Contributors

Listed alphabetically. For details and a brief history see the user's manual.

Arne Bockhorn, Alexander D. Brant, Felix P. Jentzsch, Monica Keerthipati, Guy G. F. Lemieux, Nithin S. Sabu, Tobias Wiersema

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Fine Grain FPGA Overlay Architecture and Tools

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