This material is for those who are interested in developing RTL design for FPGA.
Most of the contents are prepared by Dr. Ando Ki (andoki@gmail.com) and some of it has been collected from open source domain. So you are welcome to use it without any restrictions, but be noted that there is no support or warranty and can use it at your own risk.
Any material or subjects protected by intellectual property right, each contributor holds copyright over their respective contributions.
It is assumed that you have followings.
- Ubuntu 16 or 18 on Intel-processor PC
- Xilinx Vivado WebPack installed (no license required)
- Avent ZedBoard
- Future Design Systems CON-FMC
Vivado WebPack is a license-free Vivado software package from Xilinx for synthesis and analysis of HDL designs, More details can be found at here.
ZedBoard is a low-cost development board for the Xilinx Zynq-7000 FPGA. More details can be found at here.
CON-FMC is an FMC (FPGA Mezzanine Card) and connects computer to the FPGA through USB 3.0/2.0.
More details can be found at here
and here.
It is subject to change without notice.
Covers how to use Verilog task to test block.
Covers how to use Xilinx built-in block memory
Covers how to use clock manager
Covers general and details of Verilog
Covers system bus in general
Covers AMBA APB and memory block with APB interface
Covers GPIO with APB interface
Covers AMBA AXI bus and memory with AXI interface
Covers DMA with AXI interface
10. session_10_tea
Covers how to develop RTL from C-level algorithm using Tiny Encryption Standard
Covers how to develop fixed-point from floating-point
Covers how to use HLS
Covers 2D convolution for deep learning application
Covers pooling for deep learning application
Covers activation functions for deep learning application
16. session_16_i2c
Covers I2C controller
17. session_17_spi
Covers SPI controller
18. session_18_uart
Covers UART
Covers DDR memory interface
Covers Gigabit Ethernet MAC
Covers PCI-Express