moved from examples/test3_spi_master

git-svn-id: svn+ssh://scm.gforge.inria.fr/svn/wsim@649 c0ef0dea-404d-0410-ad65-84cceb5f200a

examples/test3/test3-spi-master/Makefile

@@ -0,0 +1,62 @@
+# makfile configuration
+NAME     = test_spi_master
+OBJECTS  = main.o uart1.o clock.o
+CPU      = msp430x1611
+INCLUDES = -I.
+CFLAGS   = -mmcu=${CPU} -O2 -Wall ${INCLUDES} -g
+
+#switch the compiler (for the internal make rules)
+CC              = msp430-gcc
+
+.PHONY: all FORCE clean download download-jtag download-bsl dist
+
+#all should be the first target. it's built when make is run without args
+all: ${NAME}.elf ${NAME}.a43 ${NAME}.lst
+
+#confgigure the next line if you want to use the serial download
+download: download-jtag
+#download: download-bsl
+
+#additional rules for files
+${NAME}.elf: ${OBJECTS}
+	${CC} -mmcu=${CPU} -o $@ ${OBJECTS}
+
+${NAME}.a43: ${NAME}.elf
+	msp430-objcopy -O ihex $^ $@
+
+${NAME}.lst: ${NAME}.elf
+	msp430-objdump -dSt $^ >$@
+
+${NAME}.dmp: ${NAME}.elf
+	msp430-objdump -d $^ >$@
+
+main.pp.c: main.c
+	${CC} -E $(CFLAGS) $^ >$@
+
+main.s: main.c
+	${CC} -S $(CFLAGS) $^ >$@
+
+download-jtag: all
+	msp430-jtag -e ${NAME}.elf
+
+download-bsl: all
+	msp430-bsl -e ${NAME}.elf
+
+clean:
+	rm -f ${NAME}.elf ${NAME}.a43 ${NAME}.lst ${OBJECTS} *.log *.vcd *.trc
+
+#backup archive
+dist:
+	tar czf dist.tgz *.c *.h *.txt makefile
+
+#dummy target as dependecy if something has to be build everytime
+FORCE:
+
+#project dependencies
+main.o: main.c
+
+uart1.o: ./uart1.c ./uart1.h
+	${CC} -c ${CFLAGS} $<
+
+clock.o: ./clock.c ./clock.h
+	${CC} -c ${CFLAGS} $<

examples/test3/test3-spi-master/clock.c

@@ -0,0 +1,165 @@
+/*
+ * Copyright  2008-2009 INRIA/SensTools
+ * 
+ * <dev-team@sentools.info>
+ * 
+ * This software is a set of libraries designed to develop applications
+ * for the WSN430 embedded hardware platform.
+ * 
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software.  You can  use, 
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info". 
+ * 
+ * As a counterpart to the access to the source code and  rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty  and the software's author,  the holder of the
+ * economic rights,  and the successive licensors  have only  limited
+ * liability. 
+ * 
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading,  using,  modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean  that it is complicated to manipulate,  and  that  also
+ * therefore means  that it is reserved for developers  and  experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or 
+ * data to be ensured and,  more generally, to use and operate it in the 
+ * same conditions as regards security. 
+ * 
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+/**
+ *  \file   clock.c
+ *  \brief  msp430 system clock 
+ *  \author Antoine Fraboulet
+ *  \date   2005
+ **/
+
+#include <io.h>
+#include <signal.h>
+#include <iomacros.h>
+#include <stdio.h>
+
+#include "clock.h"
+
+/***************************************************************
+ * we have to wait OFIFG to be sure the switch is ok 
+ * slau049e.pdf page 4-12 [pdf page 124]
+ ***************************************************************/
+
+#define WAIT_CRISTAL()                                                 \
+do {                                                                   \
+  int i;                                                               \
+  do {                                                                 \
+    IFG1 &= ~OFIFG;                  /* Clear OSCFault flag  */        \
+    for (i = 0xff; i > 0; i--)       /* Time for flag to set */        \
+       nop();                        /*                      */        \
+  }  while ((IFG1 & OFIFG) != 0);    /* OSCFault flag still set? */    \
+} while (0)
+
+/***************************************************************
+ *
+ ***************************************************************/
+
+void set_mcu_speed_dco_mclk_4MHz_smclk_1MHz(void)
+{
+  /*
+   * ACLK  = ??
+   * MCLK  = dcoclk @ 4.16MHz
+   * SMCLK = dcoclk / 2
+   */
+
+  // turn on XT1 
+
+  //start up crystall oscillator XT2
+  // DIVA_0 -> ACLK divider = 1
+  // RSEL2 | RSEL1 | RSEL0 -> resistor select
+  BCSCTL1 = XT2OFF | RSEL2 | RSEL1 | RSEL0;
+
+  // SELM_0 = dcoclk
+  // SELM_1 = dcoclk
+  // SELM_2 = XT2CLK/LFXTCLK
+  // SELM_3 = LFXTCLK
+  // SELS   : SMCLK source XT2
+  // DIVS_1 : SMCLK divider /2 
+  BCSCTL2 = SELM_0 | DIVS_2;
+
+  // dcox = 6, rsel = 7, mod = 0
+  // according to "Bob L'éponge" the MCLK clock speed should
+  // be set to 4.16MHz and SMCLK clock speed to 2.08Mhz
+  DCOCTL  = DCO2 | DCO1;
+
+  WAIT_CRISTAL();
+}
+
+/***************************************************************
+ *
+ ***************************************************************/
+
+void set_mcu_speed_xt2_mclk_2MHz_smclk_1MHz(void)
+{
+  DCOCTL   = 0; /* dco */
+  BCSCTL1  = 0; /* xt2 on + xts high + aclk full speed */
+  BCSCTL2  = (SELM_2 | DIVM_2) | (SELS | DIVS_3); /* xt2/4, xt2/8 */
+
+  WAIT_CRISTAL();
+} 
+
+/***************************************************************
+ *
+ ***************************************************************/
+
+void set_mcu_speed_xt2_mclk_4MHz_smclk_1MHz(void)
+{
+  DCOCTL   = 0;
+  BCSCTL1  = 0;
+  BCSCTL2  = (SELM_2 | DIVM_1) | (SELS | DIVS_3);
+
+  WAIT_CRISTAL();
+} 
+
+void set_aclk_div(uint16_t div)
+{
+  int f=0;
+  switch (div)
+    {
+    case 1: f = DIVA_0; break;
+    case 2: f = DIVA_1; break;
+    case 4: f = DIVA_2; break;
+    case 8: f = DIVA_3; break;
+    default: f = DIVA_0; break;
+    }
+  BCSCTL1  &= ~(DIVA_3);
+  BCSCTL1  |= f;
+}
+
+/***************************************************************
+ *
+ ***************************************************************/
+
+void set_mcu_speed_xt2_mclk_8MHz_smclk_8MHz(void)
+{
+  DCOCTL  = 0;
+  BCSCTL1 = 0;
+  BCSCTL2 = SELM_2 | SELS;
+
+  WAIT_CRISTAL();
+}
+
+/***************************************************************
+ *
+ ***************************************************************/
+
+void set_mcu_speed_xt2_mclk_8MHz_smclk_1MHz(void)
+{
+  DCOCTL  = 0;
+  BCSCTL1 = 0;
+  BCSCTL2 = SELM_2 | (SELS | DIVS_3) ;
+
+  WAIT_CRISTAL();
+}

examples/test3/test3-spi-master/clock.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright  2008-2009 INRIA/SensTools
+ * 
+ * <dev-team@sentools.info>
+ * 
+ * This software is a set of libraries designed to develop applications
+ * for the WSN430 embedded hardware platform.
+ * 
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software.  You can  use, 
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info". 
+ * 
+ * As a counterpart to the access to the source code and  rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty  and the software's author,  the holder of the
+ * economic rights,  and the successive licensors  have only  limited
+ * liability. 
+ * 
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading,  using,  modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean  that it is complicated to manipulate,  and  that  also
+ * therefore means  that it is reserved for developers  and  experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or 
+ * data to be ensured and,  more generally, to use and operate it in the 
+ * same conditions as regards security. 
+ * 
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+/**
+ *  \file   clock.h
+ *  \brief  msp430 system clock 
+ *  \author Antoine Fraboulet
+ *  \date   2005
+ **/
+
+#ifndef CLOCK_H
+#define CLOCK_H
+
+void set_mcu_speed_dco_mclk_4MHz_smclk_1MHz (void);
+
+void set_mcu_speed_xt2_mclk_2MHz_smclk_1MHz (void);
+void set_mcu_speed_xt2_mclk_4MHz_smclk_1MHz (void);
+void set_mcu_speed_xt2_mclk_8MHz_smclk_1MHz (void);
+void set_mcu_speed_xt2_mclk_8MHz_smclk_8MHz (void);
+
+/**
+ * Set the ACLK clock divider from the 32768Hz external quartz.
+ * \param div the divider, should be either 1/2/4/8
+ */
+void set_aclk_div                           (uint16_t div);
+
+#endif

examples/test3/test3-spi-master/demo.sh

@@ -0,0 +1,84 @@
+#! /bin/sh
+
+## =============Conf=====================
+WSIM=wsim-msp1611-3
+WTRC=wtracer
+WSNET1=wsnet1
+WSNET2=wsnet
+
+if [ "x`which nc.traditional`" = "x" ]
+then
+    NETCAT=nc
+else
+    NETCAT=nc.traditional
+fi
+
+# set WSNET to "--wsnet1", "--wsnet2", or "" if you are using wsim alone
+WSNET_MODE=
+WSNET2_CONF="./worldsens.xml"
+NB_NODE=1
+
+LOG="--verbose=2"
+MODE="--mode=time --modearg=10s"
+#MODE="--mode=gdb"
+UI="--ui"
+## ======================================
+
+
+## =============WSNET=====================
+if [ "$WSNET_MODE" = "--wsnet1" ]
+then
+    xterm -T ${WSNET1} -e "${WSNET1}" &
+    echo "${WSNET1}"
+else
+    if [ "$WSNET_MODE" = "--wsnet2" ]
+    then
+        xterm -T ${WSNET2} -e "${WSNET2} -c ${WSNET2_CONF}" &
+        echo "${WSNET2} -c ${WSNET2_CONF}"
+    fi
+fi
+## ======================================
+
+
+## =============NETCAT====================
+iter=0
+while [ ${iter} -lt ${NB_NODE} ]
+do
+    NC="${NETCAT} -u -p 700${iter} localhost 600${iter}"
+    xterm -T netcat-${iter} -e "${NC}" &
+    echo "${NC}"
+    iter=`expr ${iter} + 1`
+done
+## ======================================
+
+
+## =============WSIM=====================
+# --serial1_io=bk:udp:localhost:6000:localhost:7000
+WS="${WSIM} ${MODE} ${WSNET_MODE} ${LOG} ${TRC} --logfile=n0.log --trace=n0.trc --serial1_io=udp:localhost:6000:localhost:7000 ./test_spi_master.elf"
+xterm -T wsim -e "${WS}" &
+echo "${WS}"
+## ======================================
+
+
+## =============Wait=====================
+read dummyval
+## ======================================
+
+
+## =============Traces===================
+iter=0
+while [ ${iter} -lt ${NB_NODE} ]
+do
+    ${WTRC} --in=n${iter}.trc --out=n${iter}.vcd --format=vcd
+    echo "${WTRC} --in=n${iter}.trc --out=n${iter}.vcd --format=vcd"
+    iter=`expr ${iter} + 1` 
+done
+## ======================================
+
+
+## =============End======================
+killall -SIGUSR1 ${WSIM}   > /dev/null 2>&1
+killall -SIGQUIT ${WSNET}  > /dev/null 2>&1
+killall -SIGUSR1 ${NETCAT} > /dev/null 2>&1
+## ======================================
+