Release 127 of the mbed library

Ports for Upcoming Targets

2669: Added u-blox C029 target ARMmbed/mbed-os#2669
2707: [EFM32] Add IAR support for remaining Silicon Labs targets ARMmbed/mbed-os#2707
2819: MultiTech xDot platform support - 09.26.2016 ARMmbed/mbed-os#2819
2827: include MultiTech xDot in mbed 5 releases ARMmbed/mbed-os#2827

Fixes and Changes

2522: Add CThunk for CM7 ARMmbed/mbed-os#2522
2518: Enable uvisor on Beetle ARMmbed/mbed-os#2518
2571: STM32F7 - Add asynchronous serial ARMmbed/mbed-os#2571
2616: STM32F3xx - Add Serial Flow Control pins + enable it ARMmbed/mbed-os#2616
2619: NUCLEO_L152RE - Add Serial Flow Control ARMmbed/mbed-os#2619
2620: NUCLEO_F429ZI - Add SERIAL_FC macro ARMmbed/mbed-os#2620
2666: [EFM32] Microsecond ticker optimization ARMmbed/mbed-os#2666
2681: STM32F0xx - Add support of ADC internal channels ARMmbed/mbed-os#2681
2687: [NRF5] Add fs_data symbol in data secton for gcc ARMmbed/mbed-os#2687
2696: Add device_has to all nrf51 devices ARMmbed/mbed-os#2696
2703: TARGET_NRF5: Changed 'serial_baud' implementation to support special baud rates. ARMmbed/mbed-os#2703
2704: DISCO_L476VG: add SPI nicknames ARMmbed/mbed-os#2704
2723: KSDK serial_api.c: Fix assertion error for ParityEven ARMmbed/mbed-os#2723
2463: [STM32L0] Add asynchronous serial ARMmbed/mbed-os#2463
2572: Fix STM32F407VG target name and LPC11U6X linker errors ARMmbed/mbed-os#2572
2698: DELTA_DFBM_NQ620 target ARMmbed/mbed-os#2698
2542: Dev spi asynch stm32f4 ARMmbed/mbed-os#2542
2650: STM32F3 - Add low power timer ARMmbed/mbed-os#2650
2415: [STM32F0] Add asynchronous serial ARMmbed/mbed-os#2415
2585: Added support for ADC only pins in LPC43xx ARMmbed/mbed-os#2585
2622: [STM32F4] Add asynchronous I2C ARMmbed/mbed-os#2622
2719: Updated ARM linker scripts for Kinetis platforms that use SDK 2.0 ARMmbed/mbed-os#2719
2728: Added ethernet and enabled IPV4 feature for the EVK-ODIN-W2/C029 target ARMmbed/mbed-os#2728
2747: [LPC11U68] Fix pin interrupt select offset ARMmbed/mbed-os#2747
2751: STM32L0xx - Add Serial Flow Control ARMmbed/mbed-os#2751
2753: [NUCLEO_F767ZI] Add CAN capability ARMmbed/mbed-os#2753
2759: STM32F0 - Add low power timer ARMmbed/mbed-os#2759
2763: STM32L1 - Add low power timer ARMmbed/mbed-os#2763
2764: STM32L4 - Add low power timer ARMmbed/mbed-os#2764
2771: STM32L4 - Update deepsleep implementation ARMmbed/mbed-os#2771
2775: Update KSDK SDHC driver for K64F & K66F ARMmbed/mbed-os#2775
2792: [NUCLEO_F303ZE] MBED-OS5 capability ARMmbed/mbed-os#2792
2762: STM32L0 - Add low power timer ARMmbed/mbed-os#2762
2761: STM32F7 - Add low power timer ARMmbed/mbed-os#2761

CThunk.h

@@ -32,36 +32,35 @@
 #define __CTHUNK_H__
 
 #define CTHUNK_ADDRESS 1
+#define CTHUNK_VARIABLES volatile uint32_t code[2]
 
-#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)) && ! defined(__CORTEX_A9)
-#define CTHUNK_VARIABLES volatile uint32_t code[1]
+#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7) || defined(__CORTEX_A9))
 /**
-* CTHUNK disassembly for Cortex-M3/M4 (thumb2):
-* * ldm.w pc,{r0,r1,r2,pc}
+* CTHUNK disassembly for Cortex-M3/M4/M7/A9 (thumb2):
+* * adr  r0, #4
+* * ldm  r0, {r0, r1, r2, pc}
 *
 * This instruction loads the arguments for the static thunking function to r0-r2, and
 * branches to that function by loading its address into PC.
 *
 * This is safe for both regular calling and interrupt calling, since it only touches scratch registers
 * which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
 */
-#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
+#define CTHUNK_ASSIGMENT do {                              \
+                             m_thunk.code[0] = 0xE890A001; \
+                             m_thunk.code[1] = 0x00008007; \
+                         } while (0)
 
-#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) || defined(__CORTEX_A9)
+#elif (defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0))
 /*
-* CTHUNK disassembly for Cortex M0 (thumb):
-* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
-* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1)
-* * add r4,pc set up address to load arguments from (immediately following this code block) (2)
-* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function
-* * blx r3 call static thunk function
-* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function
+* CTHUNK disassembly for Cortex M0/M0+ (thumb):
+* * adr  r0, #4
+* * ldm  r0, {r0, r1, r2, r3}
+* * bx   r3
 */
-#define CTHUNK_VARIABLES volatile uint32_t code[3]
 #define CTHUNK_ASSIGMENT do {                              \
-                             m_thunk.code[0] = 0x2404B51F; \
-                             m_thunk.code[1] = 0xCC0F447C; \
-                             m_thunk.code[2] = 0xBD1F4798; \
+                             m_thunk.code[0] = 0xC80FA001; \
+                             m_thunk.code[1] = 0x00004718; \
                          } while (0)
 
 #else
@@ -225,6 +224,13 @@ class CThunk
                 __ca9u_inv_tlb_all();
                 __v7_inv_btac();
             }
+#endif
+#if defined(__CORTEX_M7)
+            /* Data cache clean and invalid */
+            SCB_CleanInvalidateDCache();
+
+            /* Instruction cache invalid */
+            SCB_InvalidateICache();
 #endif
             __ISB();
             __DSB();

TARGET_ARCH_BLE/core_cm3.h

@@ -1337,6 +1337,34 @@ typedef struct
     @{
  */
 
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* CMSIS_VECTAB_VIRTUAL */
+
 /** \brief  Set Priority Grouping
 
   The function sets the priority grouping field using the required unlock sequence.
@@ -1347,7 +1375,7 @@ typedef struct
 
     \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
@@ -1367,7 +1395,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 
     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 }
@@ -1379,7 +1407,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
   NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
@@ -1391,7 +1419,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
   NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
@@ -1407,7 +1435,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
   return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
@@ -1419,7 +1447,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
   NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
@@ -1431,7 +1459,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
   NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
@@ -1446,7 +1474,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
     \return             0  Interrupt status is not active.
     \return             1  Interrupt status is active.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
 {
   return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
@@ -1461,7 +1489,7 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
   if((int32_t)IRQn < 0) {
     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
@@ -1483,7 +1511,7 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
   if((int32_t)IRQn < 0) {

TARGET_ARCH_GPRS/core_cm3.h

@@ -1337,6 +1337,34 @@ typedef struct
     @{
  */
 
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* CMSIS_VECTAB_VIRTUAL */
+
 /** \brief  Set Priority Grouping
 
   The function sets the priority grouping field using the required unlock sequence.
@@ -1347,7 +1375,7 @@ typedef struct
 
     \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
@@ -1367,7 +1395,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 
     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 }
@@ -1379,7 +1407,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
   NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
@@ -1391,7 +1419,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
   NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
@@ -1407,7 +1435,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
   return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
@@ -1419,7 +1447,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
   NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
@@ -1431,7 +1459,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
   NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
@@ -1446,7 +1474,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
     \return             0  Interrupt status is not active.
     \return             1  Interrupt status is active.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
 {
   return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
@@ -1461,7 +1489,7 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
   if((int32_t)IRQn < 0) {
     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
@@ -1483,7 +1511,7 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
   if((int32_t)IRQn < 0) {

TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/objects.h

@@ -65,24 +65,7 @@ struct dac_s {
     uint8_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
 
-struct i2c_s {
-    I2CName  i2c;
-    uint32_t slave;
-};
 
 #include "common_objects.h"
 #include "gpio_object.h"

TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F4/common_objects.h

@@ -68,6 +68,36 @@ struct serial_s {
 #endif
 };
 
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
+};
+
+struct i2c_s {
+    I2CName  i2c;
+    I2C_HandleTypeDef handle;
+    IRQn_Type event_i2cIRQ;
+    IRQn_Type error_i2cIRQ;
+    uint8_t slave;
+#if DEVICE_I2C_ASYNCH
+    uint32_t address;
+    uint8_t event;
+    uint8_t stop;
+    uint8_t available_events;
+    uint8_t XferOperation;
+#endif
+};
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus