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enc28j60.c
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enc28j60.c
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/*! \file enc28j60.c \brief Microchip ENC28J60 Ethernet Interface Driver. */
//*****************************************************************************
//
// File Name : 'enc28j60.c'
// Title : Microchip ENC28J60 Ethernet Interface Driver
// Author : Pascal Stang (c)2005
// Created : 9/22/2005
// Revised : 9/22/2005
// Version : 0.1
// Target MCU : Atmel AVR series
// Editor Tabs : 4
//
// Description : This driver provides initialization and transmit/receive
// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.
// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin
// chip, using an SPI interface to the host processor.
//
//*****************************************************************************
#include "enc28j60.h"
#include <avr/io.h>
#if DEBUG
#include "uart.h"
#include "util.h"
#include <stdlib.h>
#endif
uint8_t Enc28j60Bank;
uint16_t NextPacketPtr;
uint8_t FlowControlEnable = 0;
#define ENC28J60_CONTROL_PORT PORTD
#define ENC28J60_CONTROL_DDR DDRD
#define ENC28J60_CONTROL_CS 4
void nicSetMacAddress(const uint8_t* macaddr) {
// write MAC address
// NOTE: MAC address in ENC28J60 is byte-backward
enc28j60Write(MAADR5, *macaddr++);
enc28j60Write(MAADR4, *macaddr++);
enc28j60Write(MAADR3, *macaddr++);
enc28j60Write(MAADR2, *macaddr++);
enc28j60Write(MAADR1, *macaddr++);
enc28j60Write(MAADR0, *macaddr++);
}
uint8_t enc28j60ReadOp(uint8_t op, uint8_t address) {
uint8_t data;
// assert CS
ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);
// issue read command
SPDR = op | (address & ADDR_MASK);
while(!(SPSR & (1<<SPIF)));
// read data
SPDR = 0x00;
while(!(SPSR & (1<<SPIF)));
// do dummy read if needed
if(address & 0x80)
{
SPDR = 0x00;
while(!(inb(SPSR) & (1<<SPIF)));
}
data = SPDR;
// release CS
ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
/*#if DEBUG
uart_puts("ReadOp: addr=0x");
char buf[8];
utoa(address, buf, 16);
uart_puts(buf);
uart_puts(" op=0x");
utoa(op, buf, 1);
uart_puts(buf);
uart_puts(" data=0x");
utoa(data, buf, 16);
uart_puts(buf);
uart_puts("\r\n");
#endif*/
return data;
}
void enc28j60WriteOp(uint8_t op, uint8_t address, uint8_t data) {
// assert CS
ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);
// issue write command
SPDR = op | (address & ADDR_MASK);
while(!(SPSR & (1<<SPIF)));
// write data
SPDR = data;
while(!(SPSR & (1<<SPIF)));
// release CS
ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
/*#if DEBUG
uart_puts("WriteOp: addr=0x");
char buf[32];
utoa(address, buf, 16);
uart_puts(buf);
uart_puts(" op=0x");
utoa(op, buf, 16);
uart_puts(buf);
uart_puts(" data=0x");
utoa(data, buf, 16);
uart_puts(buf);
uart_puts("\r\n");
#endif*/
}
void enc28j60ReadBuffer(uint16_t len, uint8_t* data) {
// assert CS
ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);
// issue read command
SPDR = ENC28J60_READ_BUF_MEM;
while(!(SPSR & (1<<SPIF)));
while(len--)
{
// read data
SPDR = 0x00;
while(!(SPSR & (1<<SPIF)));
*data++ = SPDR;
}
// release CS
ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
}
void enc28j60WriteBuffer(uint16_t len, uint8_t* data) {
// assert CS
ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);
// issue write command
SPDR = ENC28J60_WRITE_BUF_MEM;
while(!(SPSR & (1<<SPIF)));
while(len--)
{
// write data
SPDR = *data++;
while(!(SPSR & (1<<SPIF)));
}
// release CS
ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);
}
void enc28j60SetBank(uint8_t address) {
// set the bank (if needed)
if((address & BANK_MASK) != Enc28j60Bank)
{
// set the bank
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);
Enc28j60Bank = (address & BANK_MASK);
}
}
uint8_t enc28j60Read(uint8_t address)
{
// set the bank
enc28j60SetBank(address);
// do the read
return enc28j60ReadOp(ENC28J60_READ_CTRL_REG, address);
}
void enc28j60Write(uint8_t address, uint8_t data)
{
// set the bank
enc28j60SetBank(address);
// do the write
enc28j60WriteOp(ENC28J60_WRITE_CTRL_REG, address, data);
}
void enc28j60PhyWrite(uint8_t address, uint16_t data) {
// set the PHY register address
enc28j60Write(MIREGADR, address);
// write the PHY data
enc28j60Write(MIWRL, data);
enc28j60Write(MIWRH, data>>8);
// wait until the PHY write completes
while(enc28j60Read(MISTAT) & MISTAT_BUSY);
}
void enc28j60Init(void) {
// initialize I/O
ENC28J60_CONTROL_DDR |= 1<<ENC28J60_CONTROL_CS;
ENC28J60_CONTROL_PORT |= 1<<ENC28J60_CONTROL_CS;
PORTB |= 1<<PB5; //SCK HI
DDRB |= 1<<PB2 |1<<PB3 | 1<<PB5; // mosi, sck, ss output
DDRB &= ~(1<<PB4); // miso input
// initialize SPI interface
// master mode und /2x takt (klappt auch wenn der mega8 mit 16mhz läuft !!)
SPCR |= 1<<MSTR | 1<<SPE;
SPSR |= 1<<SPI2X;
// perform system reset
enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
// check CLKRDY bit to see if reset is complete
while(!(enc28j60Read(ESTAT) & ESTAT_CLKRDY));
// do bank 0 stuff
// initialize receive buffer
// 16-bit transfers, must write low byte first
// set receive buffer start address
NextPacketPtr = RXSTART_INIT;
enc28j60Write(ERXSTL, RXSTART_INIT&0xFF);
enc28j60Write(ERXSTH, RXSTART_INIT>>8);
// set receive pointer address
enc28j60Write(ERXRDPTL, RXSTART_INIT&0xFF);
enc28j60Write(ERXRDPTH, RXSTART_INIT>>8);
// set receive buffer end
// ERXND defaults to 0x1FFF (end of ram)
enc28j60Write(ERXNDL, RXSTOP_INIT&0xFF);
enc28j60Write(ERXNDH, RXSTOP_INIT>>8);
// set transmit buffer start
// ETXST defaults to 0x0000 (beginnging of ram)
enc28j60Write(ETXSTL, TXSTART_INIT&0xFF);
enc28j60Write(ETXSTH, TXSTART_INIT>>8);
// do bank 2 stuff
// enable MAC receive
enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
// bring MAC out of reset
enc28j60Write(MACON2, 0x00);
// enable automatic padding, CRC operations and full duplex (part1)
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN|MACON3_FULDPX);
// set inter-frame gap (non-back-to-back)
enc28j60Write(MAIPGL, 0x12);
enc28j60Write(MAIPGH, 0x0C);
// set inter-frame gap (back-to-back)
enc28j60Write(MABBIPG, 0x12);
// Set the maximum packet size which the controller will accept
enc28j60Write(MAMXFLL, MAX_FRAMELEN&0xFF);
enc28j60Write(MAMXFLH, MAX_FRAMELEN>>8);
// do bank 3 stuff
// write MAC address
// NOTE: MAC address in ENC28J60 is byte-backward
enc28j60Write(MAADR5, ENC28J60_MAC0);
enc28j60Write(MAADR4, ENC28J60_MAC1);
enc28j60Write(MAADR3, ENC28J60_MAC2);
enc28j60Write(MAADR2, ENC28J60_MAC3);
enc28j60Write(MAADR1, ENC28J60_MAC4);
enc28j60Write(MAADR0, ENC28J60_MAC5);
// no loopback of transmitted frames
enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS);
// full duplex (part2)
enc28j60PhyWrite(PHCON1, PHCON1_PDPXMD);
// set up some filters. We accept unicasts and broadcasts, but only if their CRC is ok (see page 47/chapter 8 of the manual)
enc28j60Write(ERXFCON, ERXFCON_UCEN | ERXFCON_BCEN | ERXFCON_CRCEN);
// maximum pause time for flow control
enc28j60Write(EPAUSL, 0xFF);
enc28j60Write(EPAUSH, 0xFF);
// switch to bank 0
enc28j60SetBank(ECON1);
// enable interrutps
// enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
// enable packet reception
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
}
void enc28j60PacketSend(uint16_t len, unsigned char* packet) {
// Set the write pointer to start of transmit buffer area
enc28j60Write(EWRPTL, TXSTART_INIT);
enc28j60Write(EWRPTH, TXSTART_INIT>>8);
// Set the TXND pointer to correspond to the packet size given
enc28j60Write(ETXNDL, (TXSTART_INIT+len));
enc28j60Write(ETXNDH, (TXSTART_INIT+len)>>8);
// write per-packet control byte
enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
// copy the packet into the transmit buffer
enc28j60WriteBuffer(len, packet);
// send the contents of the transmit buffer onto the network
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
/* if(enc28j60Read()) {
uart_puts("Error occured why transmitting package\r\n");
}*/
}
uint16_t enc28j60PacketReceive(uint16_t maxlen, unsigned char* packet, uint16_t *rxstat) {
uint16_t len;
// check if a packet has been received and buffered
if(!(enc28j60Read(EIR) & EIR_PKTIF))
return 0;
// Make absolutely certain that any previous packet was discarded
//if( WasDiscarded == FALSE)
// MACDiscardRx();
// Set the read pointer to the start of the received packet (AUTOINC?)
enc28j60Write(ERDPTL, (NextPacketPtr));
enc28j60Write(ERDPTH, (NextPacketPtr)>>8);
// read the next packet pointer
NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
// read the packet length
len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
// read the receive status
*rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
*rxstat |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8;
if(*rxstat & RXSTAT_LONG_DROP_EVENT) {
uart_puts("PACKET DROPPED! (or \"long event)\"\r\n");
}
// limit retrieve length
// (we reduce the MAC-reported length by 4 to remove the CRC)
len = MIN(len, maxlen);
// copy the packet from the receive buffer
enc28j60ReadBuffer(len, packet);
// Move the RX read pointer to the start of the next received packet
// This frees the memory we just read out
enc28j60Write(ERXRDPTL, (NextPacketPtr));
enc28j60Write(ERXRDPTH, (NextPacketPtr)>>8);
// decrement the packet counter indicate we are done with this packet
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
uint8_t pkt_cnt = enc28j60Read(EPKTCNT);
if(!FlowControlEnable && pkt_cnt > 16) {
enc28j60FlowControl(1);
} else if (FlowControlEnable && pkt_cnt < 10) {
enc28j60FlowControl(0);
}
if(enc28j60Read(EIR) & EIR_RXERIF) {
uart_puts("there was a receive error\r\n");
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_RXERIF);
}
char buf[8];
utoa(pkt_cnt, buf, 10);
uart_puts(buf);
uart_puts(" packets in rx buf\r\n");
return len;
}
void enc28j60FlowControl(uint8_t enable) {
// manual page 56
if(enable) {
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EFLOCON, 0x02);
uart_puts("flow control enabled\r\n");
} else {
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EFLOCON, 0x03);
uart_puts("flow control disabled\r\n");
}
FlowControlEnable = enable;
}