A comparative study of 6T SRAM with 6T SE-SRAM cell

Table of Contents

• Methodology
• Standard 6T SRAM cell
  • Block Diagram
  • Pre-Layout Simulation
  • Layout
• SE-SRAM cell
  • Block Diagram
  • Pre-Layout Simulation
  • Layout
• Comparative analysis between standard 6T with SE-SRAM cell
• Conclusion
• Contributor
• Acknowledgement

Methodology

• Memory size:- 1k X 32-bit
• Operating voltage:- 5V
• Used Techonology:- 0.5um SCMOS technique
• Access time:- <30ns
• Tools used:- NGSpice, Magic, Sue2

Standard 6T SRAM cell

The standard 6T SRAM cell consists of two back to back inverter for storing the data and two access transistors for read and write operation.

Block diagram

Pre-Layout Simulation

layout

Layout has been done by open-source layout tool Magic.

SE-SRAM cell

The single-ended 6T SRAM cell consists of two cross-coupled inverters connected to bitline(BL) with an access transistor (M5) and a data storage node isolation transistor (M6). For Read operation, a read assist transistor(Mra) is connected with an M6 transistor. One of the Inverter consists of a write assist transistor (Mwa) as shown in the figure. The read operation is controlled by the read assist transistor (Mra) by giving an input R. Similarly, the write operation is controlled by the write assist transistor (Mwa) and access transistor (M5) which depends upon the input W0 and WL.

Block Diagram

Pre-layout simulation

Layout

Comparative analysis between standard 6t with SE-SRAM cell

SNM (Static Noise Margin):-

6T SRAM cell

SE-SRAM cell

Read SNM for different PVT corners

The single ended 6T bitcell provides 4.5X higher worst-case read SNM as compared to the standard 6T SRAM bitcell under the same process variations.

Write-stability

The write trip point voltage of a proposed 6T is 28% (1.4V) higher than the standard 6T. Thus the single ended 6T design has a little bit of high write ability than the standard 6T design. However, it has an advantage since an erroneous write will not take place easily compared to standard 6T cell.

Conclusion

This project presents a 6T SE-SRAM cell. In the proposed 6T SE SRAM Cell :

• Read current path is isolated from the data storage node Q and QB and, hence less vulnerable to noise.
• Isolation of read current path improves the SNM > 4x compared to standard 6T Cell
• Strong write ability compared to standard 6T cell using MOSIS 0.5um CMOS technology.

Contributor

• Vikash kumar

Acknowledgement

• Dr.Saroj Rout, Associate Professor, Silicon Institute of Technology
• Mr.Santunu sarangi, Assistant professor, Silicon Institute of Technology