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at hand, it has onboard VGA, doesn't have onboard PS/2 (I could probably wire a PS/2 connector externaly), but I also found an USB keyboard demo: https://github.com/Digilent/Nexys-A7-100T-Keyboard/tree/master
Which if I understands corecly allows you to connect USB keyboard to FPGA and it would convert it to PS/2 scancodes
Or I could always use SerialTerminal if PS/2 doesn't work 😄
If I understand everything to port this to my board I just need to define inputs and outputs and I should at least have a picture from VGA display at first (if input doesn't work yet)
What I am very confused is how to open this project in Vivado (if thats even possible)
Thanks for Anwsering and Best Regards
The text was updated successfully, but these errors were encountered:
you will most likely have to create a project and then import the verilog into it. There are other examples within the boards section of other people using different tools. But ultimately this project tries to be as generic as possible to allow you to use it however you need.
While I can't help you, I don't think it will be too difficult to get it to work.
Hello there, I saw your awesome project and just happen to have this Nexys A7 FPGA: https://digilent.com/shop/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/
at hand, it has onboard VGA, doesn't have onboard PS/2 (I could probably wire a PS/2 connector externaly), but I also found an USB keyboard demo: https://github.com/Digilent/Nexys-A7-100T-Keyboard/tree/master
Which if I understands corecly allows you to connect USB keyboard to FPGA and it would convert it to PS/2 scancodes
Or I could always use SerialTerminal if PS/2 doesn't work 😄
If I understand everything to port this to my board I just need to define inputs and outputs and I should at least have a picture from VGA display at first (if input doesn't work yet)
What I am very confused is how to open this project in Vivado (if thats even possible)
Thanks for Anwsering and Best Regards
The text was updated successfully, but these errors were encountered: