forked from VLSI-EDA/PoC
/
.gitignore
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/
.gitignore
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# general file excludes
~*.tmp
~*.docx
*~
*.o
~$*
# ignore Python caches
__pycache__
# ignore files in netlist/
/netlist/
!/netlist/configuration.ini
!/netlist/netlist.ps1
!/netlist/netlist.sh
!/netlist/template.cgc
# ignore folders
/temp/
/vSim/
# ignore files from PoC
/py/config.private.ini
/tb/common/my_project.vhdl
# ignore external tool files: ActiveHDL, QuestaSim
/prj/ActiveHDL/*
/prj/ActiveHDL/*.*
/prj/ActiveHDL/**/*.*
!/prj/ActiveHDL/PoC.adf
!/prj/ActiveHDL/PoC.wsp
/prj/Diamond/*.*
/prj/Diamond/*/*
/prj/Diamond/**/*.*
!/prj/Diamond/**/*.lpf
!/prj/Diamond/*.ldf
!/prj/Diamond/*.sty
!/prj/Diamond/*.vhdl
/prj/QuestaSim/*
/prj/QuestaSim/*.*
/prj/QuestaSim/**/*.*
!/prj/QuestaSim/PoC.mpf
# ignore Xilinx ISE files
/other/ise/**/*.*
/other/ise/**/ise
!/other/ise/**/*.xise
!/other/ise/**/*.xpr
!/other/ise/**/iseconfig/filter.filter
!/other/ise/**/*.qpf
!/other/ise/**/*.qsf
# ignore Quartus files
/other/quartus/**/*.*
/other/quartus/**/db/
/other/quartus/**/incremental_db/
/other/quartus/**/output_files/
/other/quartus/**/simulation/
/other/quartus/**/greybox_tmp/
!/other/quartus/**/*.qpf
!/other/quartus/**/*.qsf
!/other/quartus/**/*.vhdl
#ignore Vivado files
/other/vivado/**/*.cache
/other/vivado/**/*.hw
/other/vivado/**/*.runs
/other/vivado/**/*.sim
/other/vivado/**/*.ip_user_files
# general whitelist
!.git*
!.publish
!.README.md