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Progetto_Reti_Logiche_2020

Authors

887630 Giuseppe Serra (@pepser) giuseppe.serra@mail.polimi.it

890219 Alessandro Zito (@alessandrozito98) alessandro4.zito@mail.polimi.it

Description of the project can be found here.

Specific document can be found here.

Histogram Equalization

The component required had to receive a 8-bit pixels of an image as input and calculate the new pixel value by following the specifications in "Histogram Equalitazion" method.

This project has been developed as part of the "Reti Logiche" course at Politecnico di Milano. It has been evaluated "30/30" cum Laude.

Input Format

The program expects its input from stdio with the following format. It receives from RAM in the first two addressed the number of the rows and then columns. From the tird address, it receives the pixels values to convert.

Example of the input stream:

signal RAM: ram_type := (0 => std_logic_vector(to_unsigned(  2  , 8)), 
                         1 => std_logic_vector(to_unsigned(  2  , 8)), 
                         2 => std_logic_vector(to_unsigned(  46  , 8)),  
                         3 => std_logic_vector(to_unsigned(  131  , 8)), 
                         4 => std_logic_vector(to_unsigned(  62  , 8)), 
                         5 => std_logic_vector(to_unsigned(  89  , 8)), 
                         others => (others =>'0'));

Expected output

0
255
64
72

Testing Result

The testing platform was divided in public and private tests. Public tests can be found here. The results of some public tests is written in the final report.

However, i also tested my program using a test generator written by me and other students. The original repo can be found here. There is also a test generator written by another supervisor, called Fabio Salice that I didn't used. You can find it here.