Skip to content
View alfadelta10010's full-sized avatar
⚙️
Building
⚙️
Building

Highlights

  • Pro

Organizations

@MUNSoc-PESUECC
Block or Report

Block or report alfadelta10010

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. pes-asic-class pes-asic-class Public

    Assignments and Files from the ASIC course

    Verilog

  2. alpha-processor alpha-processor Public

    Basic Single Stage RISC-V 32-bit processor

    SystemVerilog 1

  3. RISCV-Processor RISCV-Processor Public

    Single Stage RISC-V 32-bit Processor made in RISC-V Lab UE21EC352A - RISC-V Architecture

    SystemVerilog

  4. pesu-bot-2025 pesu-bot-2025 Public

    Forked from sach-12/pesu-bot

    PES'25 server's take on 2019 server's PESU bot

    Python 2 35