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  • Hyderabad
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alokvishwa10/README.md
  • 👋 Hi, I’m @alokvishwa10
  • 👀 I’m interested in Digital VLSI design and Verification, IP verification and SOC level verification.
  • 😎 I am Proficient in Digital Electronics, Verilog, SystemVerilog, UVM, PERL Scripting, LINUX & UNIX commands, VIM Editor, C language, AMBA protocols and SPI - UART - I2C protocols
  • 🌱 Completed my Masters' in Microelectronics form IIIT Allahabad
  • 💞️ I’m looking to collaborate on New designs, Verification projects, Protocols.
  • 💰 Currently seeking opportunities to enter the VLSI industry, Learn from experts and Explore new possibilities.
  • 📫 Reach me at alokvishwa10@gmail.com or DM me at https://www.linkedin.com/in/alok-vishwakarma-7732b41b0/

Pinned

  1. 32-bit-Risc-Processor 32-bit-Risc-Processor Public

    This repo has all the files needed for simulation of a 32-bit RISC processor, which is built based on 5 stages of pipeline that can handle Arithmetic, logical and load-store operations for now.

    Verilog

  2. Design-and-Verification-of-SPI-protocol Design-and-Verification-of-SPI-protocol Public

    Design and Verification of SPI protocol

    SystemVerilog

  3. Elevator-design-using-FSM Elevator-design-using-FSM Public

    Design and simulation of FSM based Elevator in Xilinx Vivado

    Verilog 1

  4. Master-Slave-D-Flip-Flop Master-Slave-D-Flip-Flop Public

  5. Secret-media-enryption-and-decryption-over-image Secret-media-enryption-and-decryption-over-image Public

    B.tech Mini project

    MATLAB 1

  6. Synchronous-FIFO Synchronous-FIFO Public

    Verilog