sm_soc_devkit_ghrd: add discrepancy file from sm_ghrd branch

Signed-off-by: Wong, Felix Siew An <felix.siew.an.wong@intel.com>

sm_soc_devkit_ghrd/Makefile

@@ -433,10 +433,8 @@ QUARTUS_TCL_ARGS += f2h_width 0
 QSYS_TCL_CMDS += set f2h_width 0;
 endif
 
-QSYS_TCL_CMDS += set proj_root $(PROJECT_ROOT);
-QUARTUS_TCL_ARGS += proj_root $(PROJECT_ROOT)
-
-$(info $(QUARTUS_TCL_ARGS))
+QSYS_TCL_CMDS += set prjroot $(PROJECT_ROOT);
+QUARTUS_TCL_ARGS += prjroot $(PROJECT_ROOT)
 
 QSYS_TCL_CMDS += set dfl_rom_en $(DFL_ROM_EN);
 QUARTUS_TCL_ARGS += dfl_rom_en $(DFL_ROM_EN)
@@ -798,8 +796,14 @@ endif
 HELP_TARGETS += generate_from_tcl
 generate_from_tcl.HELP := Generate the Quartus Project and Qsys design files from tcl script source
 
+.PHONY: writeback_user_config
+writeback_user_config:
+	@$(ECHO) $(USER_CONFIG_UPDATE) > $(BUILD_DIR)/config.tmp
+	@$(AWK) -v output=$(USER_CONFIG_FILE) -f $(GHRD_SCRIPT_CONFIG_FTM_FILE)  $(BUILD_DIR)/config.tmp
+	@$(RM) -rf $(BUILD_DIR)/config.tmp
+
 .PHONY: generate_from_tcl
-generate_from_tcl: generate_submodule $(INTEL_CUSTOM_IP_DIR_TARGET)
+generate_from_tcl: writeback_user_config generate_submodule $(INTEL_CUSTOM_IP_DIR_TARGET)
 	@$(MAKE) qsys_generate_qsys
 	@$(ECHO) "generate_from_tcl done!"
 

sm_soc_devkit_ghrd/arguments_solver.tcl

@@ -102,7 +102,6 @@
 #
 #****************************************************************************
 
-
 source ${prjroot}/design_config.tcl 
 
 # proc check_then_accept { param } {
@@ -167,17 +166,9 @@ if { ![ info exists board_pwrmgt ] } {
 }
 
 # Loading Board default configuration settings
-<<<<<<< HEAD
-<<<<<<< HEAD
-set board_config_file "${prjroot}/board/board_${board}_config.tcl"
-=======
-set board_config_file $proj_root/board/board_${board}_config.tcl
-puts "board path: $board_config_file"
->>>>>>> b561674... Fix TCL linkage to needed files, reposition Makefile.new as default, enable HPS_EMIF as default on.
-=======
-#set board_config_file "${prjroot}/board/board_${board}_config.tcl"
-set board_config_file "./board/board_${board}_config.tcl"
->>>>>>> 31c9302... For old makefile flow
+set board_config_file ${prjroot}/board/board_${board}_config.tcl
+puts "\[GHRD:info\] \$board_config_file: $board_config_file"
+
 if {[file exist $board_config_file]} {
     source $board_config_file
 } else {
@@ -750,26 +741,8 @@ if {$f2s_address_width > 32 && $f2sdram_width > 0} {
     set cct_en 0
 }
 
-<<<<<<< HEAD
-
-<<<<<<< HEAD
-source ${prjroot}/agilex_hps_pinmux_solver.tcl
-source ${prjroot}/agilex_hps_parameter_solver.tcl
-source ${prjroot}/agilex_hps_io48_delay_chain_solver.tcl
-=======
-source $proj_root/hps_subsys/agilex_hps_pinmux_solver.tcl
-source $proj_root/hps_subsys/agilex_hps_parameter_solver.tcl
-source $proj_root/hps_subsys/agilex_hps_io48_delay_chain_solver.tcl
->>>>>>> b561674... Fix TCL linkage to needed files, reposition Makefile.new as default, enable HPS_EMIF as default on.
-=======
-#source ${prjroot}/agilex_hps_pinmux_solver.tcl
-#source ${prjroot}/agilex_hps_parameter_solver.tcl
-#source ${prjroot}/agilex_hps_io48_delay_chain_solver.tcl
-source ./agilex_hps_pinmux_solver.tcl
-source ./agilex_hps_parameter_solver.tcl
-source ./agilex_hps_io48_delay_chain_solver.tcl
->>>>>>> 31c9302... For old makefile flow
-
-# Was thinking to enable single TCL entry for flow of TOP RTL, qsys, quartus generation. Ideal still pending implementation
-# exec quartus_sh --script=create_ghrd_quartus.tcl $top_quartus_arg
-# exec qsys-script --script=create_ghrd_qsys.tcl --quartus-project=$project_name.qpf --cmd="$qsys_arg"
+source $prjroot/hps_subsys/agilex_hps_pinmux_solver.tcl
+source $prjroot/hps_subsys/agilex_hps_parameter_solver.tcl
+source $prjroot/hps_subsys/agilex_hps_io48_delay_chain_solver.tcl
+
+

sm_soc_devkit_ghrd/board/board_DK-A5E065BB32AES1_emif_setting.tcl

@@ -8,7 +8,7 @@
 # This script hosts Default EMIF IP settings for the Agilex SoC Devkit board.
 #
 #****************************************************************************
-source $proj_root/utils.tcl
+source $prjroot/utils.tcl
 
 if {$hps_emif_en == 1} {
 set total_hps_emif_width $hps_emif_width

sm_soc_devkit_ghrd/create_ghrd_quartus.tcl

@@ -94,18 +94,6 @@ set_global_assignment -name HPS_INITIALIZATION "HPS FIRST"
 set_global_assignment -name HPS_INITIALIZATION "AFTER INIT_DONE"
 }
 
-if {$config_scheme == "ACTIVE SERIAL X4"} {
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
-} elseif {$config_scheme == "AVST X8"} {
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8"
-} elseif {$config_scheme == "AVST X16"} {
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X16"
-} elseif {$config_scheme == "AVST X32"} {
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X32"
-}
-
-
-
 if {$hps_dap_mode == 1} {
 set_global_assignment -name HPS_DAP_SPLIT_MODE "HPS PINS"
 } elseif {$hps_dap_mode == 2} {

sm_soc_devkit_ghrd/create_ghrd_top.tcl

@@ -209,4 +209,4 @@ close $template_fh
 set content [altera_terp $template param]
 set fo [open "./ghrd_timing.sdc" "w"] 
 puts $fo $content
-close $fo
+close $fo

sm_soc_devkit_ghrd/design_config.tcl

@@ -55,11 +55,6 @@ set USER0_CLK_SRC_SELECT 0
 set USER1_CLK_SRC_SELECT 0
 set USER0_CLK_FREQ 500
 set USER1_CLK_FREQ 500
-
-## ----------------
-## HPS EMIF
-## ----------------
-
 set HPS_F2H_IRQ_EN 0
 set F2H_FREE_CLK_EN 0
 # Option to enable HPS EMIF

sm_soc_devkit_ghrd/hps_subsys/agilex_hps_pinmux_solver.tcl

@@ -1,7 +1,7 @@
 #****************************************************************************
 #
 # SPDX-License-Identifier: MIT-0
-# Copyright(c) 2019-2020 Intel Corporation.
+# Copyright(c) 2019-2023 Intel Corporation.
 #
 #****************************************************************************
 #
@@ -135,9 +135,7 @@ for {set i 0} {$i < 12} {incr i} {
     lappend io48_q4_assignment NONE
 }
 
-#puts "prjroot = ${prjroot} "
-#source ${prjroot}/agilex_io48.tcl
-source ./agilex_io48.tcl
+source ${prjroot}/hps_subsys/agilex_io48.tcl
 
 # Assigning individual IO48 peripherals
 if {$hps_jtag_en == 1} {
@@ -150,7 +148,7 @@ if {$hps_sdmmc4b_q1_en == 1} {
 	set io48_q1_assignment [lreplace $io48_q1_assignment 0 2 SDMMC:DATA0 SDMMC:DATA1 SDMMC:CLK]
 }
 if {$hps_sdmmc4b_q1_sel_en == 1} {
-		set io48_q1_assignment [lreplace $io48_q1_assignment 3 3 SDMMC:LVL_SEL]
+	set io48_q1_assignment [lreplace $io48_q1_assignment 3 3 SDMMC:LVL_SEL]
 }
 if {$hps_sdmmc4b_q1_alt_en == 1} {
 	set io48_q1_assignment [lreplace $io48_q1_assignment 4 4 SDMMC:WRITE_PROTECT]
@@ -510,6 +508,6 @@ if {$hps_io_custom != ""} {
 }
 
 #puts "[llength $io48_q1_assignment]"
-puts "Sorted IO48 assignment:\n$io48_q1_assignment\n$io48_q2_assignment\n$io48_q3_assignment\n$io48_q4_assignment\n"
+puts "\[GHRD:info\] Sorted IO48 assignment:\n$io48_q1_assignment\n$io48_q2_assignment\n$io48_q3_assignment\n$io48_q4_assignment\n"
 
 

sm_soc_devkit_ghrd/hps_subsys/construct_subsys_hps.tcl

@@ -1,25 +1,23 @@
 #****************************************************************************
 #
 # SPDX-License-Identifier: MIT-0
-# Copyright(c) 2019-2021 Intel Corporation.
+# Copyright(c) 2019-2023 Intel Corporation.
 #
 #****************************************************************************
 #
-# This script construct sub system of HPS for higher level integration
-# This tcl will be invoke by create_ghrd_qsys.tcl 
-# This tcl script basically contained only configuration settings for HPS & HPS EMIF, connections between HPS & HPS EMIF
+# This script construct Hard Processor subsystem for higher level integration later.
+# The Makefile in $prjroot folder will pass in variable needed by this TCL as defined
+# in the subsystem Makefile automatically. User will have the ability to modify the 
+# defined variable dynamically during (MAKE) target flow of generate_from_tcl.
 #
 #****************************************************************************
 set currentdir [pwd]
 set foldername [file tail $currentdir]
 puts "\[GHRD:info\] Directory name: $foldername"
 
-#puts "prjroot = ${prjroot} "
-#source ${prjroot}/arguments_solver.tcl
-#source ${prjroot}/utils.tcl
-
-source ./arguments_solver.tcl
-source ./utils.tcl
+puts "\[GHRD:info\] \$prjroot = ${prjroot}"
+source ${prjroot}/arguments_solver.tcl
+source ${prjroot}/utils.tcl
 
 set subsys_name $foldername
 

sm_soc_devkit_ghrd/jtag_subsys/construct_subsys_jtag_master.tcl

@@ -1,16 +1,16 @@
 #****************************************************************************
 #
 # SPDX-License-Identifier: MIT-0
-# Copyright(c) 2019-2020 Intel Corporation.
+# Copyright(c) 2019-2023 Intel Corporation.
 #
 #****************************************************************************
 #
-# This script construct JTAG AVMM MAster sub system for higher level integration
-# The GHRD create_ghrd_qsys.tcl will call each of those subsystem construct script
-# automatically based on the corresponding parameter argument defined
+# This script construct JTAG AVMM MAster subsystem for higher level integration later.
+# The Makefile in $prjroot folder will pass in variable needed by this TCL as defined
+# in the subsystem Makefile automatically. User will have the ability to modify the 
+# defined variable dynamically during (MAKE) target flow of generate_from_tcl.
 #
 #****************************************************************************
-
 set currentdir [pwd]
 set foldername [file tail $currentdir]
 puts "\[GHRD:info\] Directory name: $foldername"
@@ -72,10 +72,10 @@ export hps_m master hps_m_master
 
 
 # interconnect requirements
-set_domain_assignment {$system} {qsys_mm.clockCrossingAdapter} {AUTO}
-set_domain_assignment {$system} {qsys_mm.maxAdditionalLatency} {1}
-set_domain_assignment {$system} {qsys_mm.enableEccProtection} {FALSE}
-set_domain_assignment {$system} {qsys_mm.insertDefaultSlave} {FALSE}
+#set_domain_assignment {$system} {qsys_mm.clockCrossingAdapter} {AUTO}
+#set_domain_assignment {$system} {qsys_mm.maxAdditionalLatency} {1}
+#set_domain_assignment {$system} {qsys_mm.enableEccProtection} {FALSE}
+#set_domain_assignment {$system} {qsys_mm.insertDefaultSlave} {FALSE}
 
 sync_sysinfo_parameters 
 

sm_soc_devkit_ghrd/peripheral_subsys/construct_subsys_peripheral.tcl

@@ -1,13 +1,14 @@
 #****************************************************************************
 #
 # SPDX-License-Identifier: MIT-0
-# Copyright(c) 2019-2021 Intel Corporation.
+# Copyright(c) 2019-2023 Intel Corporation.
 #
 #****************************************************************************
 #
-# This script construct sub system of PCIe for higher level integration
-# The GHRD create_ghrd_qsys.tcl will call each of those subsystem construct script
-# automatically based on the corresponding parameter argument defined
+# This script construct Peripherals subsystem for higher level integration later.
+# The Makefile in $prjroot folder will pass in variable needed by this TCL as defined
+# in the subsystem Makefile automatically. User will have the ability to modify the 
+# defined variable dynamically during (MAKE) target flow of generate_from_tcl.
 #
 #****************************************************************************
 set currentdir [pwd]

sm_soc_devkit_ghrd/top_level_sdc_template.sdc.terp

@@ -20,9 +20,9 @@ create_clock -name EMIF_REF_CLOCK -period $hps_emif_ref_clk_freq_ns [get_ports e
 @@
 @@## This is required as the HPS SDC is not working for hps_user_clk constraints. HSDES: 1507301642
 @@#create_clock -name hps_user_clk -period 2.5 [get_pins {soc_inst|agilex_hps|intel_agilex_hps_inst|fpga_interfaces|hps_inst|s2f_module|s2f_user_clk1_hio}]
+
 set_false_path -from [get_ports {fpga_reset_n[0]}]
 @@#set_input_delay -clock MAIN_CLOCK 1 [get_ports {fpga_reset_n[0]}]
-@@}
 
 # sourcing JTAG related SDC
 source ./jtag.sdc
@@ -52,24 +52,6 @@ set_false_path -from * -to [get_ports {fpga_led_pio[2]}]
 set_false_path -from * -to [get_ports {fpga_led_pio[3]}]
 @@}
 @@}
-<<<<<<< HEAD
-
-@@if {$hps_sgmii_en == 1} {
-# EMAC MDIO constraints
-@@  for {set m $hps_sgmii_emac_start_node} {$m<=$hps_sgmii_emac_end_node} {incr m} {
-set_max_skew -to [get_ports "emac${m}_mdc"] 2
-set_max_skew -to [get_ports "emac${m}_mdio"] 2
-set_false_path -from * -to [ get_ports emac${m}_phy_rst_n ]
-set_false_path -from [get_ports {emac${m}_phy_irq}] -to *
-@@  }
-@@}
-
-@@if {$hbm_en != 1} { 
-# False Path between debounced and reset synchronizer
-set_false_path -from fpga_reset_n_debounced -to {soc_inst|rst_controller_*|altera_reset_synchronizer_int_chain[1]}
-@@}
-=======
 
 # False Path between debounced and reset synchronizer
 set_false_path -from fpga_reset_n_debounced -to {soc_inst|rst_controller_*|altera_reset_synchronizer_int_chain[1]}
->>>>>>> 5678b26... Update the EMIF IP parameterization