correct power management, SDC

Signed-off-by: Ong, Lean Kim <lean.kim.ong@intel.com>
altera-opensource · Mar 28, 2024 · 0809313 · 0809313
1 parent f4cd84b
commit 0809313
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Showing 4 changed files with 25 additions and 13 deletions.
diff --git a/sm_soc_devkit_ghrd/Makefile b/sm_soc_devkit_ghrd/Makefile
@@ -29,10 +29,7 @@
 #       - Agilex5: none [default]
 #
 #   QUARTUS_DEVICE:
-#       - A5ED065BB32AE5SR0: none [default]
-#
-#   BOARD_PWRMGT:
-#       - enpirion: none [default]
+#       - A5ED065BB32AE5SR0: FPGA OPN# [default]
 #
 #   ENABLE_HPS_EMIF_ECC:
 #       - 0: disable [default]
@@ -201,8 +198,8 @@ ENABLE_HPS_EMIF_ECC ?= 0
 QUARTUS_DEVICE_FAMILY := Agilex5
 #SM
 QUARTUS_DEVICE ?= A5ED065BB32AE5SR0
-# Board Power Management. Support board devkit is supported: linear, enpirion
-BOARD_PWRMGT ?= enpirion
+# Board Power Management. temporary set power management IC type here, till an alternative is made available for Agilex5 devkit
+BOARD_PWRMGT ?= linear
 # Publicly Available DC: devkit_dc_oobe, devkit_dc_nand, devkit_dc_emmc
 DAUGHTER_CARD ?= devkit_dc_oobe
 

diff --git a/sm_soc_devkit_ghrd/board/board_DK-A5E065BB32AES1_config.tcl b/sm_soc_devkit_ghrd/board/board_DK-A5E065BB32AES1_config.tcl
@@ -55,16 +55,16 @@ proc config_pwrmgt {} {
     global board_pwrmgt
     if {$board_pwrmgt == "linear"} {
         # Linear tech
-        set_global_assignment -name INI_VARS "ASM_ENABLE_ADVANCED_DEVICES=ON;"
+        #set_global_assignment -name INI_VARS "ASM_ENABLE_ADVANCED_DEVICES=ON;"
         set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
         set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
-        set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
+        set_global_assignment -name USE_PWRMGT_SDA SDM_IO16
         set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
         set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
         set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER
-        set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42
-        set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 43
-        set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 44
+        set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74
+        set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 75
+        set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
         set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
         set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
         set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00

diff --git a/sm_soc_devkit_ghrd/create_ghrd_quartus.tcl b/sm_soc_devkit_ghrd/create_ghrd_quartus.tcl
@@ -43,7 +43,6 @@ foreach hdlfile $hdlfilelist {
 set_global_assignment -name IP_SEARCH_PATHS "intel_custom_ip/**/*;custom_ip/**/*"
 
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name SDC_FILE ghrd_timing.sdc
 
 # #HSDES 2207525670: User Reset Gate IP
 # set_global_assignment -name DISABLE_REGISTER_POWERUP_INITIALIZATION ON
@@ -501,4 +500,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_gpio1_io${io_num}
 }
 }
 
+set_global_assignment -name SDC_FILE ghrd_timing.sdc
+
 project_close
diff --git a/sm_soc_devkit_ghrd/ghrd_timing.sdc b/sm_soc_devkit_ghrd/ghrd_timing.sdc
@@ -15,7 +15,7 @@ set_time_format -unit ns -decimal_places 3
 create_clock -name MAIN_CLOCK -period 10 [get_ports fpga_clk_100]
 create_clock -name EMIF_REF_CLOCK -period 6.0 [get_ports emif_hps_emif_ref_clk_0_clk]
 
-set_false_path -from [get_ports {fpga_reset_n[0]}]
+set_false_path -from [get_ports {fpga_reset_n}]
 
 # sourcing JTAG related SDC
 source ./jtag.sdc
@@ -42,3 +42,17 @@ set_false_path -from * -to [get_ports {fpga_led_pio[3]}]
 set_false_path -from fpga_reset_n_debounced -to {soc_inst|rst_controller_*|altera_reset_synchronizer_int_chain[1]}
 
 
+create_generated_clock -name emac0_phy_txclk_o_hio_from_i2_5 -master_clock [get_clocks 2_5m_3mux1] -source [get_pins {soc_inst|subsys_hps|agilex_hps|intel_agilex_5_soc_inst|sm_hps|sundancemesa_hps_inst|emac0_phy_txclk_i}] [get_pins {soc_inst|subsys_hps|agilex_hps|intel_agilex_5_soc_inst|sm_hps|sundancemesa_hps_inst|emac0_phy_txclk_o_hio}] -add
+create_generated_clock -name emac0_phy_txclk_o_hio_from_i25  -master_clock [get_clocks 25m_3mux1]  -source [get_pins {soc_inst|subsys_hps|agilex_hps|intel_agilex_5_soc_inst|sm_hps|sundancemesa_hps_inst|emac0_phy_txclk_i}] [get_pins {soc_inst|subsys_hps|agilex_hps|intel_agilex_5_soc_inst|sm_hps|sundancemesa_hps_inst|emac0_phy_txclk_o_hio}] -add
+create_generated_clock -name emac0_phy_txclk_o_hio_from_i125 -source [get_registers {soc_inst|subsys_hps|agilex_hps|intel_agilex_5_soc_inst|sm_hps|sundancemesa_hps_inst~emac0_rgmii_txclk_cm.reg}] [get_pins {soc_inst|subsys_hps|agilex_hps|intel_agilex_5_soc_inst|sm_hps|sundancemesa_hps_inst|emac0_phy_txclk_o_hio}] -add
+set_clock_groups -logically_exclusive -group emac0_phy_txclk_o_hio_from_i2_5 -group emac0_phy_txclk_o_hio_from_i25 -group emac0_phy_txclk_o_hio_from_i125
+
+set_clock_groups -logically_exclusive -group [ get_clocks emac0_phy_txclk_o_hio_from_i125 ] -group [ get_clocks 250m_3mux1] -group [ get_clocks 25m_3mux1] -group [ get_clocks 2_5m_3mux1]
+set_clock_groups -logically_exclusive -group [ get_clocks emac0_phy_txclk_o_hio_from_i25 ] -group [ get_clocks 250m_3mux1] -group [ get_clocks 2_5m_3mux1] -group [ get_clocks 25m_3mux1]
+set_clock_groups -logically_exclusive -group [ get_clocks emac0_phy_txclk_o_hio_from_i2_5 ] -group [ get_clocks 250m_3mux1] -group [ get_clocks 25m_3mux1] -group [ get_clocks 2_5m_3mux1]
+
+set_false_path -from * -to [get_keepers -no_duplicates {soc_inst|subsys_fpga_rgmii|intel_gmii_to_rgmii_converter_0|intel_gmii_to_rgmii_converter_inst|u_intel_gmii_to_rgmii_adapter_core|u_rx_clk_reset_even_sync|din_sync_2}]
+set_false_path -from * -to [get_keepers -no_duplicates {soc_inst|subsys_fpga_rgmii|intel_gmii_to_rgmii_converter_0|intel_gmii_to_rgmii_converter_inst|u_intel_gmii_to_rgmii_adapter_core|u_rx_clk_reset_even_sync|din_sync_1}]
+
+#set_false_path -from [get_keepers -no_duplicates {soc_inst|subsys_fpga_rgmii|intel_gmii_to_rgmii_converter_0|intel_gmii_to_rgmii_converter_inst|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out}] -to [get_keepers -no_duplicates {soc_inst|subsys_fpga_rgmii|intel_gmii_to_rgmii_converter_0|intel_gmii_to_rgmii_converter_inst|u_intel_gmii_to_rgmii_adapter_core|u_rx_clk_reset_even_sync|din_sync_2}]
+#set_false_path -from [get_keepers -no_duplicates {soc_inst|subsys_fpga_rgmii|intel_gmii_to_rgmii_converter_0|intel_gmii_to_rgmii_converter_inst|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out}] -to [get_keepers -no_duplicates {soc_inst|subsys_fpga_rgmii|intel_gmii_to_rgmii_converter_0|intel_gmii_to_rgmii_converter_inst|u_intel_gmii_to_rgmii_adapter_core|u_rx_clk_reset_even_sync|din_sync_1}]