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Use subfolder name as subsystem name
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Signed-off-by: Ong, Lean Kim <lean.kim.ong@intel.com>
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@lekong-pg @FelixWongSiewAn
lekong-pg authored and FelixWongSiewAn committed Mar 28, 2024
1 parent 48ac46d commit 088aa9c
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Showing 8 changed files with 128 additions and 103 deletions.
14 changes: 8 additions & 6 deletions sm_soc_devkit_ghrd/Makefile
View file
Expand Up @@ -93,7 +93,6 @@ QUARTUS_PGM := quartus_pgm
QSYS_GENERATE := qsys-generate
QSYS_SCRIPT := qsys-script


# Helpful Macros
SPACE := $(empty) $(empty)

Expand All @@ -107,15 +106,15 @@ endif

USER_CONFIG := $(shell sed 's/[[:space:]]//g' build/config)
define LOAD_USER_CONFIG
$(firstword $(subst =, $(SPACE), $1)) := $(word 2, $(subst =, $(SPACE), $1))
$(firstword $(subst =, $(SPACE), $1)) := $(word 2, $(subst =, $(SPACE), $1))
endef
$(foreach p, $(USER_CONFIG), $(eval $(call LOAD_USER_CONFIG, $p)))

# update user-specific configuration
USER_CONFIG_UPDATE :=
define UPDATE_USER_CONFIG
$(firstword $(subst =, $(SPACE), $1)) := $$($(firstword $(subst =, $(SPACE), $1)))
USER_CONFIG_UPDATE += $(firstword $(subst =, $(SPACE), $1))=$$($(firstword $(subst =, $(SPACE), $1)))
$(firstword $(subst =, $(SPACE), $1)) := $$($(firstword $(subst =, $(SPACE), $1)))
USER_CONFIG_UPDATE += $(firstword $(subst =, $(SPACE), $1))=$$($(firstword $(subst =, $(SPACE), $1)))
endef
$(foreach p, $(USER_CONFIG), $(eval $(call UPDATE_USER_CONFIG, $p)))

Expand Down Expand Up @@ -283,8 +282,9 @@ QUARTUS_TCL_ARGS += proj_root $(PROJECT_ROOT)

# Merge QSYS_TCL_CMDS into a single QSys arg
ifneq ($(QSYS_TCL_CMDS),)
QSYS_TCL_ARGS += --cmd="$(QSYS_TCL_CMDS)"
QSYS_TCL_ARGS += $(QSYS_TCL_CMDS)
endif
#QSYS_TCL_ARGS += --cmd="$(QSYS_TCL_CMDS)"

#===============================================
# Building modules control
Expand All @@ -293,6 +293,8 @@ MODULES := $(shell cat $(MODULES_FILE))
MODULE_BUILD := $(foreach n, $(MODULES), $(n).build)

$(MODULE_BUILD): quartus_generate_qsf_qpf quartus_generate_top
$(info to send qsys_tcl_arg is $(QSYS_TCL_ARGS))
$(info to send user_config_update is $(USER_CONFIG_UPDATE))
@$(MAKE) QSYS_ARGS='$(QSYS_ARGS)' QSYS_TCL_ARGS='$(QSYS_TCL_ARGS)' $(USER_CONFIG_UPDATE) -C $(subst .build,,$@) generate_from_tcl

.PHONY: generate_submodule
Expand Down Expand Up @@ -616,7 +618,7 @@ QSYS_GEN_QSYS_DEPS += quartus_generate_qsf_qpf
ifneq ($(QSYS_QSYS_GEN),)
qsys_generate_qsys: $(QSYS_QSYS_GEN) $(INTEL_CUSTOM_IP_DIR_TARGET)
@$(RM) $(QSYS_FILE_TOP)
qsys-script $(QSYS_ARGS) --script=$< $(QSYS_TCL_ARGS)
qsys-script $(QSYS_ARGS) --script=$< --cmd="$(QSYS_TCL_ARGS)"
ifeq ($(HPS_ENABLE_SGMII),1)
$(MAKE) quartus_add_post_sgmii_sdc
endif
Expand Down
84 changes: 42 additions & 42 deletions sm_soc_devkit_ghrd/create_ghrd_qsys.tcl
View file
Expand Up @@ -103,27 +103,27 @@ add_component_param "altera_address_span_extender ext_hps_m_master
"

if {$hps_en == 1} {
add_instance hps_subsys subsys_hps
add_instance subsys_hps hps_subsys
reload_ip_catalog
}

if {$fpga_peripheral_en == 1} {
add_instance periph_subsys subsys_periph
add_instance subsys_periph peripheral_subsys
reload_ip_catalog
}

if {$jtag_ocm_en == 1} {
add_instance jtg_mst subsys_jtg_mst
add_instance subsys_debug jtag_subsys
reload_ip_catalog
}


connect " clk_100.out_clk ext_hps_m_master.clock
rst_in.out_reset ext_hps_m_master.reset"

connect_map " jtg_mst.hps_m_master ext_hps_m_master.windowed_slave 0x0 "
#connect_map " ext_hps_m_master.expanded_master hps_subsys.fpga2hps 0x1_0000_0000 "
connect_map " ext_hps_m_master.expanded_master hps_subsys.f2sdram 0x0000 "
connect_map " subsys_debug.hps_m_master ext_hps_m_master.windowed_slave 0x0 "
#connect_map " ext_hps_m_master.expanded_master subsys_hps.fpga2hps 0x1_0000_0000 "
connect_map " ext_hps_m_master.expanded_master subsys_hps.f2sdram 0x0000 "

if {$cct_en == 1} {
connect " clk_100.out_clk intel_cache_coherency_translator_0.clock
Expand All @@ -137,43 +137,43 @@ if {$cct_en == 1} {
}

if {$f2s_address_width >32} {
connect_map "jtg_mst.hps_m_master ext_hps_m_master.windowed_slave 0x0"
connect_map "subsys_debug.hps_m_master ext_hps_m_master.windowed_slave 0x0"
connect_map "ext_hps_m_master.expanded_master intel_cache_coherency_translator_0.s0 0x0"
} else {
connect_map "jtg_mst.hps_m_master intel_cache_coherency_translator_0.s0 0x0"
connect_map "subsys_debug.hps_m_master intel_cache_coherency_translator_0.s0 0x0"
}

connect_map " intel_cache_coherency_translator_0.m0 hps_subsys.fpga2hps 0x0000 "
connect_map " hps_subsys.lwhps2fpga intel_cache_coherency_translator_0.csr "
connect_map " jtg_mst.fpga_m_master intel_cache_coherency_translator_0.csr 0x10200 "
connect_map " intel_cache_coherency_translator_0.m0 subsys_hps.fpga2hps 0x0000 "
connect_map " subsys_hps.lwhps2fpga intel_cache_coherency_translator_0.csr "
connect_map " subsys_debug.fpga_m_master intel_cache_coherency_translator_0.csr 0x10200 "
}

# --------------- Connections and connection parameters ------------------#

if {$hps_en == 1} {
if {$hps_emif_en == 1} {
connect "clk_100.out_clk hps_subsys.clk
rst_in.out_reset hps_subsys.reset
connect "clk_100.out_clk subsys_hps.clk
rst_in.out_reset subsys_hps.reset
"
}
if {$f2sdram_width > 0} {
connect " clk_100.out_clk hps_subsys.f2sdram_clk
rst_in.out_reset hps_subsys.f2sdram_rst
connect " clk_100.out_clk subsys_hps.f2sdram_clk
rst_in.out_reset subsys_hps.f2sdram_rst
"
}
if {$lwh2f_width > 0} {
connect " clk_100.out_clk hps_subsys.lwhps2fpga_clk
rst_in.out_reset hps_subsys.lwhps2fpga_rst
connect " clk_100.out_clk subsys_hps.lwhps2fpga_clk
rst_in.out_reset subsys_hps.lwhps2fpga_rst
"
}
if {$h2f_width > 0} {
connect " clk_100.out_clk hps_subsys.hps2fpga_clk
rst_in.out_reset hps_subsys.hps2fpga_rst
connect " clk_100.out_clk subsys_hps.hps2fpga_clk
rst_in.out_reset subsys_hps.hps2fpga_rst
"
}
if {$f2s_data_width > 0} {
connect " clk_100.out_clk hps_subsys.fpga2hps_clk
rst_in.out_reset hps_subsys.fpga2hps_rst
connect " clk_100.out_clk subsys_hps.fpga2hps_clk
rst_in.out_reset subsys_hps.fpga2hps_rst
"
}

Expand All @@ -184,68 +184,68 @@ if {$jtag_ocm_en == 1} {
connect " clk_100.out_clk ocm.clk1
rst_in.out_reset ocm.reset1
"
connect_map " jtg_mst.fpga_m_master ocm.axi_s1 0x40000 "
connect_map " subsys_debug.fpga_m_master ocm.axi_s1 0x40000 "
}
}

if {$jtag_ocm_en == 1} {
connect " clk_100.out_clk jtg_mst.clk
rst_in.out_reset jtg_mst.reset
connect " clk_100.out_clk subsys_debug.clk
rst_in.out_reset subsys_debug.reset
"
}

#if {$fpga_peripheral_en == 1} {
# connect_map " jtg_mst.fpga_m_master periph_subsys.control_slave 0x10000"
# connect_map " subsys_debug.fpga_m_master subsys_periph.control_slave 0x10000"
#}

if {$fpga_peripheral_en == 1} {
connect "clk_100.out_clk periph_subsys.clk
rst_in.out_reset periph_subsys.reset
connect "clk_100.out_clk subsys_periph.clk
rst_in.out_reset subsys_periph.reset
"
}

if {$fpga_peripheral_en == 1} {
if {$fpga_button_pio_width >0} {
# connect "agilex_hps.f2h_irq0 periph.button_pio_irq"
# set_connection_parameter_value agilex_hps.f2h_irq0/periph.button_pio_irq irqNumber {1}
# connect "periph_subsys.ILC_irq periph_subsys.button_pio_irq"
# set_connection_parameter_value periph_subsys.ILC_irq/periph_subsys.button_pio_irq irqNumber {1}
# connect "subsys_periph.ILC_irq subsys_periph.button_pio_irq"
# set_connection_parameter_value subsys_periph.ILC_irq/subsys_periph.button_pio_irq irqNumber {1}
}
if {$fpga_dipsw_pio_width >0} {
# connect "agilex_hps.f2h_irq0 periph.dipsw_pio_irq"
# set_connection_parameter_value agilex_hps.f2h_irq0/periph.dipsw_pio_irq irqNumber {0}
# connect "periph_subsys.ILC_irq periph_subsys.dipsw_pio_irq"
# set_connection_parameter_value periph_subsys.ILC_irq/periph_subsys.dipsw_pio_irq irqNumber {0}
# connect "subsys_periph.ILC_irq subsys_periph.dipsw_pio_irq"
# set_connection_parameter_value subsys_periph.ILC_irq/subsys_periph.dipsw_pio_irq irqNumber {0}
}
}

if {$h2f_width > 0} {
if {$h2f_width > 0 && $jtag_ocm_en == 1} {
connect_map "hps_subsys.hps2fpga ocm.axi_s1 0x0000"
connect_map "subsys_hps.hps2fpga ocm.axi_s1 0x0000"
}
}

if {$lwh2f_width > 0} {
#if {$jtag_ocm_en == 1} {
# connect_map "hps_subsys.lwhps2fpga periph_subsys.control_slave 0x1_0000"
# connect_map "subsys_hps.lwhps2fpga subsys_periph.control_slave 0x1_0000"
#}

if {$fpga_peripheral_en == 1} {
connect_map "hps_subsys.lwhps2fpga periph_subsys.pb_cpu_0_s0 0x20000"
connect_map "subsys_hps.lwhps2fpga subsys_periph.pb_cpu_0_s0 0x20000"
}
}

# ---------------- Exported Interfaces ----------------------------------------#
export clk_100 in_clk clk_100
export rst_in in_reset reset
export user_rst_clkgate_0 ninit_done ninit_done
export hps_subsys usb31_io usb31_io
export hps_subsys hps_io hps_io
export subsys_hps usb31_io usb31_io
export subsys_hps hps_io hps_io

if {$hps_emif_en == 1} {
export hps_subsys emif_hps_emif_mem_0 emif_hps_emif_mem_0
export hps_subsys emif_hps_emif_oct_0 emif_hps_emif_oct_0
export hps_subsys emif_hps_emif_ref_clk_0 emif_hps_emif_ref_clk_0
export subsys_hps emif_hps_emif_mem_0 emif_hps_emif_mem_0
export subsys_hps emif_hps_emif_oct_0 emif_hps_emif_oct_0
export subsys_hps emif_hps_emif_ref_clk_0 emif_hps_emif_ref_clk_0
}

if {$clk_gate_en == 1} {
Expand All @@ -255,13 +255,13 @@ export clkctrl_0 clkctrl_output clkctrl_output

if {$fpga_peripheral_en == 1} {
if {$fpga_button_pio_width >0} {
export periph_subsys button_pio_external_connection button_pio_external_connection
export subsys_periph button_pio_external_connection button_pio_external_connection
}
if {$fpga_dipsw_pio_width >0} {
export periph_subsys dipsw_pio_external_connection dipsw_pio_external_connection
export subsys_periph dipsw_pio_external_connection dipsw_pio_external_connection
}
if {$fpga_led_pio_width >0} {
export periph_subsys led_pio_external_connection led_pio_external_connection
export subsys_periph led_pio_external_connection led_pio_external_connection
}
}

Expand Down
15 changes: 9 additions & 6 deletions sm_soc_devkit_ghrd/hps_subsys/Makefile
View file
Expand Up @@ -32,20 +32,23 @@ EMPTY :=
ENABLE := 1
DISABLE := 0


CURRENT_FOLDER := $(lastword $(subst $(SLASH), $(SPACE),$(PWD)))
PROJECT_ROOT := $(PWD)/../
GHRD_CONFIG_FILE := $(PROJECT_ROOT)/build/config.hps_subsys
GHRD_HELP_FILE := $(PROJECT_ROOT)/build/help.hps_subsys
GHRD_CONFIG_FILE := $(PROJECT_ROOT)/build/config.$(CURRENT_FOLDER)
GHRD_HELP_FILE := $(PROJECT_ROOT)/build/help.$(CURRENT_FOLDER)
GHRD_SCRIPT_FILE := $(PROJECT_ROOT)/scripts/config_parzer.awk

$(info folder name is $(CURRENT_FOLDER))
$(info received qsys_tcl_arg is $(QSYS_TCL_ARGS))

.PHONY: generate_from_tcl
generate_from_tcl:
ifeq ($(HPS_EN), $(ENABLE))
@qsys-script $(shell echo $(QSYS_ARGS) | sed 's/quartus-project=/quartus-project=..\//g') --script=./construct_subsys_hps.tcl $(QSYS_TCL_ARGS)
@qsys-script $(shell echo $(QSYS_ARGS) | sed 's/quartus-project=/quartus-project=..\//g') --script=./construct_subsys_hps.tcl --cmd="$(QSYS_TCL_ARGS)"
else
@echo "hps_subsys does not be enabled, skip."
@echo "$(CURRENT_FOLDER) does not be enabled, skip."
endif
@echo "generate_from_tcl for hps_subsys done!"
@echo "generate_from_tcl for $(CURRENT_FOLDER) done!"

.PHONY: config
config:
Expand Down
20 changes: 12 additions & 8 deletions sm_soc_devkit_ghrd/hps_subsys/construct_subsys_hps.tcl
View file
Expand Up @@ -10,6 +10,9 @@
# This tcl script basically contained only configuration settings for HPS & HPS EMIF, connections between HPS & HPS EMIF
#
#****************************************************************************
set currentdir [pwd]
set foldername [file tail $currentdir]
puts "\[GHRD:info\] Directory name: $foldername"

#puts "prjroot = ${prjroot} "
#source ${prjroot}/arguments_solver.tcl
Expand All @@ -18,7 +21,7 @@
source ./arguments_solver.tcl
source ./utils.tcl

set subsys_name subsys_hps
set subsys_name $foldername

package require -exact qsys 19.1

Expand Down Expand Up @@ -47,13 +50,13 @@ add_component_param "altera_reset_bridge sub_rst_in
add_component_param "intel_agilex_5_soc agilex_hps
IP_FILE_PATH ip/$subsys_name/agilex_hps.ip
MPU_EVENTS_Enable 0
GP_Enable 0
Debug_APB_Enable 0
GP_Enable 0
Debug_APB_Enable 0
STM_Enable 0
JTAG_Enable 0
CTI_Enable 0
DMA_PeriphID 0
DMA_Enable No
JTAG_Enable 0
CTI_Enable 0
DMA_PeriphID 0
DMA_Enable No
HPS_IO_Enable {$io48_q1_assignment $io48_q2_assignment $io48_q3_assignment $io48_q4_assignment}
H2F_Width $h2f_width
H2F_Address_Width $h2f_addr_width
Expand Down Expand Up @@ -91,7 +94,8 @@ if {$hps_emif_en == 1} {
connect "sub_clk.out_clk sub_rst_in.clk"

connect "agilex_hps.emif0_csr_axi emif_hps.s0_axil"
}
}

#load_component agilex_hps
#for {set i 0} {$i < 48} {incr i} {
#set_component_parameter_value IO_INPUT_DELAY${i} $input_dly_chain_io48(${i})
Expand Down
25 changes: 17 additions & 8 deletions sm_soc_devkit_ghrd/jtag_subsys/Makefile
View file
Expand Up @@ -8,7 +8,7 @@
################## USER TOPLEVEL CONFIGURATION ##########################
#
# <-
# JTAG_EN :
# SUB_DEBUG_EN :
# - 0: disable
# - 1: enable [default]
# ->
Expand All @@ -21,21 +21,30 @@ PWD := $(shell pwd)
EMPTY :=
ENABLE := 1
DISABLE := 0
SLASH := /
SPACE :=


CURRENT_FOLDER := $(lastword $(subst $(SLASH), $(SPACE),$(PWD)))
PROJECT_ROOT := $(PWD)/../
GHRD_CONFIG_FILE := $(PROJECT_ROOT)/build/config.jtag_subsys
GHRD_HELP_FILE := $(PROJECT_ROOT)/build/help.jtag_subsys
GHRD_CONFIG_FILE := $(PROJECT_ROOT)/build/config.$(CURRENT_FOLDER)
GHRD_HELP_FILE := $(PROJECT_ROOT)/build/help.$(CURRENT_FOLDER)
GHRD_SCRIPT_FILE := $(PROJECT_ROOT)/scripts/config_parzer.awk

$(info folder name is $(CURRENT_FOLDER))
$(info received qsys_tcl_arg is $(QSYS_TCL_ARGS))

#SUB_QSYS_TCL_ARG += set current_folder $(CURRENT_FOLDER);
#QSYS_TCL_ARGS += set current_folder $(CURRENT_FOLDER);
#$(info ammended qsys_tcl_arg is $(QSYS_TCL_ARGS))

.PHONY: generate_from_tcl
generate_from_tcl:
ifeq ($(JTAG_EN), $(ENABLE))
@qsys-script $(shell echo $(QSYS_ARGS) | sed 's/quartus-project=/quartus-project=..\//g') --script=./construct_subsys_jtag_master.tcl $(QSYS_TCL_ARGS)
ifeq ($(SUB_DEBUG_EN), $(ENABLE))
@qsys-script $(shell echo $(QSYS_ARGS) | sed 's/quartus-project=/quartus-project=..\//g') --script=./construct_subsys_jtag_master.tcl --cmd="$(QSYS_TCL_ARGS)"
else
@echo "jtag_subsys does not be enabled, skip."
@echo "$(CURRENT_FOLDER) does not be enabled, skip."
endif
@echo "generate_from_tcl for jtag_subsys!"
@echo "generate_from_tcl for $(CURRENT_FOLDER)!"

.PHONY: config
config:
Expand Down

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