sm_soc_devkit_ghrd: Move qsys span extender into debug_en, remove not…

… relevant error message Signed-off-by: Wong, Felix Siew An <felix.siew.an.wong@intel.com>
altera-opensource · Mar 28, 2024 · 2277f16 · 2277f16
1 parent 8ba6c3e
commit 2277f16
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Showing 5 changed files with 80 additions and 79 deletions.
diff --git a/sm_soc_devkit_ghrd/board/board_DK-A5E065BB32AES1_emif_setting.tcl b/sm_soc_devkit_ghrd/board/board_DK-A5E065BB32AES1_emif_setting.tcl
@@ -24,24 +24,24 @@ if {$fpga_emif_ecc_en} {
 }
 
 # Derive TCL and WTCL for default DDR4 mode
-if {$hps_emif_mem_part == "default_part"} {
-   if {$hps_emif_mem_clk_freq_mhz == 800} {
-      set selected_tcl 14
-      set selected_wtcl 11
-   } elseif {$hps_emif_mem_clk_freq_mhz == 1200} {
-      if {$board == "DK-SI-AGF014E" } {
-         set selected_tcl 20
-         set selected_wtcl 16
-      } else {
-         set selected_tcl 21
-         set selected_wtcl 16
-      }
-   } else {
-      puts "\"$hps_emif_mem_clk_freq_mhz\"is not a Not Supported DDR4 MEM CLK FREQ"
-      set selected_tcl 0
-      set selected_wtcl 0
-   }
-}
+# if {$hps_emif_mem_part == "default_part"} {
+   # if {$hps_emif_mem_clk_freq_mhz == 800} {
+      # set selected_tcl 14
+      # set selected_wtcl 11
+   # } elseif {$hps_emif_mem_clk_freq_mhz == 1200} {
+      # if {$board == "DK-SI-AGF014E" } {
+         # set selected_tcl 20
+         # set selected_wtcl 16
+      # } else {
+         # set selected_tcl 21
+         # set selected_wtcl 16
+      # }
+   # } else {
+      # puts "\"$hps_emif_mem_clk_freq_mhz\"is not a Not Supported DDR4 MEM CLK FREQ"
+      # set selected_tcl 0
+      # set selected_wtcl 0
+   # }
+# }
   ## DEVKIT
   # ------ Component configuration --------------------- #
 

diff --git a/sm_soc_devkit_ghrd/board/board_bbr_emif_setting.tcl b/sm_soc_devkit_ghrd/board/board_bbr_emif_setting.tcl
@@ -40,24 +40,24 @@ if {$fpga_emif_ecc_en} {
 }
 
 # Derive TCL and WTCL for default DDR4 mode
-if {$hps_emif_mem_part == "default_part"} {
-   if {$hps_emif_mem_clk_freq_mhz == 800} {
-      set selected_tcl 14
-      set selected_wtcl 11
-   } elseif {$hps_emif_mem_clk_freq_mhz == 1200} {
-      if {$board == "DK-SI-AGF014E" } {
-         set selected_tcl 20
-         set selected_wtcl 16
-      } else {
-         set selected_tcl 21
-         set selected_wtcl 16
-      }
-   } else {
+# if {$hps_emif_mem_part == "default_part"} {
+   # if {$hps_emif_mem_clk_freq_mhz == 800} {
+      # set selected_tcl 14
+      # set selected_wtcl 11
+   # } elseif {$hps_emif_mem_clk_freq_mhz == 1200} {
+      # if {$board == "DK-SI-AGF014E" } {
+         # set selected_tcl 20
+         # set selected_wtcl 16
+      # } else {
+         # set selected_tcl 21
+         # set selected_wtcl 16
+      # }
+   # } else {
       # puts "\"$hps_emif_mem_clk_freq_mhz\"is not a Not Supported DDR4 MEM CLK FREQ"
-      set selected_tcl 0
-      set selected_wtcl 0
-   }
-}
+      # set selected_tcl 0
+      # set selected_wtcl 0
+   # }
+# }
   ## DEVKIT
   # ------ Component configuration --------------------- #
 

diff --git a/sm_soc_devkit_ghrd/board/board_cvr_emif_setting.tcl b/sm_soc_devkit_ghrd/board/board_cvr_emif_setting.tcl
@@ -24,24 +24,24 @@ if {$fpga_emif_ecc_en} {
 }
 
 # Derive TCL and WTCL for default DDR4 mode
-if {$hps_emif_mem_part == "default_part"} {
-   if {$hps_emif_mem_clk_freq_mhz == 800} {
-      set selected_tcl 14
-      set selected_wtcl 11
-   } elseif {$hps_emif_mem_clk_freq_mhz == 1200} {
-      if {$board == "DK-SI-AGF014E" } {
-         set selected_tcl 20
-         set selected_wtcl 16
-      } else {
-         set selected_tcl 21
-         set selected_wtcl 16
-      }
-   } else {
-      puts "\"$hps_emif_mem_clk_freq_mhz\"is not a Not Supported DDR4 MEM CLK FREQ"
-      set selected_tcl 0
-      set selected_wtcl 0
-   }
-}
+# if {$hps_emif_mem_part == "default_part"} {
+   # if {$hps_emif_mem_clk_freq_mhz == 800} {
+      # set selected_tcl 14
+      # set selected_wtcl 11
+   # } elseif {$hps_emif_mem_clk_freq_mhz == 1200} {
+      # if {$board == "DK-SI-AGF014E" } {
+         # set selected_tcl 20
+         # set selected_wtcl 16
+      # } else {
+         # set selected_tcl 21
+         # set selected_wtcl 16
+      # }
+   # } else {
+      # puts "\"$hps_emif_mem_clk_freq_mhz\"is not a Not Supported DDR4 MEM CLK FREQ"
+      # set selected_tcl 0
+      # set selected_wtcl 0
+   # }
+# }
   ## DEVKIT
   # ------ Component configuration --------------------- #
 

diff --git a/sm_soc_devkit_ghrd/board/board_lbm_emif_setting.tcl b/sm_soc_devkit_ghrd/board/board_lbm_emif_setting.tcl
@@ -40,24 +40,24 @@ if {$fpga_emif_ecc_en} {
 }
 
 # Derive TCL and WTCL for default DDR4 mode
-if {$hps_emif_mem_part == "default_part"} {
-   if {$hps_emif_mem_clk_freq_mhz == 800} {
-      set selected_tcl 14
-      set selected_wtcl 11
-   } elseif {$hps_emif_mem_clk_freq_mhz == 1200} {
-      if {$board == "DK-SI-AGF014E" } {
-         set selected_tcl 20
-         set selected_wtcl 16
-      } else {
-         set selected_tcl 21
-         set selected_wtcl 16
-      }
-   } else {
-      puts "\"$hps_emif_mem_clk_freq_mhz\"is not a Not Supported DDR4 MEM CLK FREQ"
-      set selected_tcl 0
-      set selected_wtcl 0
-   }
-}
+# if {$hps_emif_mem_part == "default_part"} {
+   # if {$hps_emif_mem_clk_freq_mhz == 800} {
+      # set selected_tcl 14
+      # set selected_wtcl 11
+   # } elseif {$hps_emif_mem_clk_freq_mhz == 1200} {
+      # if {$board == "DK-SI-AGF014E" } {
+         # set selected_tcl 20
+         # set selected_wtcl 16
+      # } else {
+         # set selected_tcl 21
+         # set selected_wtcl 16
+      # }
+   # } else {
+      # puts "\"$hps_emif_mem_clk_freq_mhz\"is not a Not Supported DDR4 MEM CLK FREQ"
+      # set selected_tcl 0
+      # set selected_wtcl 0
+   # }
+# }
   ## DEVKIT
   # ------ Component configuration --------------------- #
 

diff --git a/sm_soc_devkit_ghrd/create_ghrd_qsys.tcl b/sm_soc_devkit_ghrd/create_ghrd_qsys.tcl
@@ -107,14 +107,6 @@ if {$f2s_address_width > 32} {
 	}
 }
 
-add_component_param "altera_address_span_extender ext_hps_f2sdram_master
-                    IP_FILE_PATH ip/$qsys_name/ext_hps_f2sdram_master.ip
-                    BURSTCOUNT_WIDTH 1
-                    MASTER_ADDRESS_WIDTH 33
-                    SLAVE_ADDRESS_WIDTH 30
-                    ENABLE_SLAVE_PORT 0
-                    MAX_PENDING_READS 1
-                    "
 if {$sub_fpga_rgmii_en == 1} {
 add_instance subsys_fpga_rgmii fpga_rgmii_subsys
 reload_ip_catalog
@@ -135,6 +127,15 @@ add_instance subsys_debug jtag_subsys
 reload_ip_catalog
 
 if { $f2sdram_width > 0 } {	
+add_component_param "altera_address_span_extender ext_hps_f2sdram_master
+                    IP_FILE_PATH ip/$qsys_name/ext_hps_f2sdram_master.ip
+                    BURSTCOUNT_WIDTH 1
+                    MASTER_ADDRESS_WIDTH 33
+                    SLAVE_ADDRESS_WIDTH 30
+                    ENABLE_SLAVE_PORT 0
+                    MAX_PENDING_READS 1
+                    "
+
 connect "         clk_100.out_clk                        ext_hps_f2sdram_master.clock
                   rst_in.out_reset                       ext_hps_f2sdram_master.reset"