make f2s bridge as axi4 instead of ace-lite

Signed-off-by: Ong, Lean Kim <lean.kim.ong@intel.com>

sm_soc_devkit_ghrd/hps_subsys/construct_subsys_hps.tcl

@@ -65,7 +65,7 @@ add_component_param "intel_agilex_5_soc agilex_hps
 					 f2sdram_address_width $f2sdram_addr_width
 					 f2s_data_width $f2s_data_width
 					 f2s_address_width $f2h_addr_width
-					 f2s_mode acelite
+					 f2s_mode axi4
                      LWH2F_Width $lwh2f_width
 					 LWH2F_Address_Width $lwh2f_addr_width
                      EMIF_AXI_Enable $hps_emif_en