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Enabled the LPDDR4 for CVR MUDV
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Signed-off-by: y <hui1.teng.lim@intel.com>
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@hui1teng @FelixWongSiewAn
hui1teng authored and FelixWongSiewAn committed Mar 28, 2024
1 parent 1616d22 commit 83359ee
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Showing 7 changed files with 105 additions and 113 deletions.
3 changes: 2 additions & 1 deletion sm_soc_devkit_ghrd/Makefile
View file
Expand Up @@ -13,6 +13,7 @@
# <-
# BOARD_TYPE:
# - hidden: hidden type [default]
# - crv: crv
#
# BOOTS_FIRST:
# - hps: hps first [default]
Expand Down Expand Up @@ -166,7 +167,7 @@ endif
# QUARTUS_DEVICE to Board Revision Mapping

# User Settings
# Valid BOARD_TYPE: devkit, pcie_devkit
# Valid BOARD_TYPE: hidden, crv
BOARD_TYPE ?= hidden
#Loading board configuration
include board/board_$(BOARD_TYPE)_make_config.inc
Expand Down
30 changes: 12 additions & 18 deletions sm_soc_devkit_ghrd/board/board_crv_emif_setting.tcl
View file
Expand Up @@ -56,9 +56,6 @@ if {$hps_emif_mem_part == "custom"} {

if {$hps_emif_type == "ddr4"} {
load_component emif_hps
#apply_component_preset "DDR4-3200U CL18 Component 1CS 16Gb (1Gb x16)"
#apply_component_preset "DDR4-3200AA CL22 Component 1CS 8Gb (512Mb x16)"
#save_component

set_component_param "emif_hps
MEM_TECHNOLOGY_AUTO_BOOL false
Expand All @@ -73,28 +70,25 @@ if {$hps_emif_mem_part == "custom"} {
MEM_DEVICE_DQ_WIDTH 16
MEM_COMPS_PER_RANK 2
"
set_component_param "emif_hps USER_EXTRA_PARAMETERS BYTE_SWIZZLE_CH0=0,X,X,X,1,2,3,X;PIN_SWIZZLE_CH0_DQS0=0,2,6,4,1,3,5,7;PIN_SWIZZLE_CH0_DQS1=12,15,8,11,14,10,13,9;PIN_SWIZZLE_CH0_DQS2=20,16,18,22,23,17,19,21;PIN_SWIZZLE_CH0_DQS3=26,30,28,24,25,27,31,29; "
} elseif {$hps_emif_type == "lpddr4"} {
load_component emif_hps

set_component_param "emif_hps
MEM_TECHNOLOGY_AUTO_BOOL false
MEM_TECHNOLOGY MEM_TECHNOLOGY_LPDDR4
HPS_EMIF_CONFIG_AUTO_BOOL false
HPS_EMIF_CONFIG HPS_EMIF_1x32
MEM_FORMAT MEM_FORMAT_DISCRETE
MEM_TOPOLOGY MEM_TOPOLOGY_FLYBY
CTRL_ECC_MODE CTRL_ECC_MODE_DISABLED
PHY_AC_PLACEMENT_AUTO_BOOL true
PHY_AC_PLACEMENT PHY_AC_PLACEMENT_BOT
MEM_DEVICE_DQ_WIDTH 16
MEM_COMPS_PER_RANK 2
MEM_PRESET_ID_AUTO_BOOL false
"
apply_component_preset "LPDDR4-2667 CL24 Component Single-Channel 1R 2CPR 16Gb (32Gb Total) x32 CK 1200.0 MHz"
save_component
HPS_EMIF_CONFIG_AUTO_BOOL false
HPS_EMIF_CONFIG HPS_EMIF_1x16
MEM_FORMAT MEM_FORMAT_DISCRETE
MEM_TOPOLOGY MEM_TOPOLOGY_FLYBY
CTRL_ECC_MODE CTRL_ECC_MODE_DISABLED
PHY_AC_PLACEMENT_AUTO_BOOL true
PHY_AC_PLACEMENT PHY_AC_PLACEMENT_BOT
MEM_DEVICE_DQ_WIDTH 16
MEM_NUM_RANKS 1
MEM_COMPS_PER_RANK 1
"
}
#PHY_MEMCLK_FREQ_MHZ 199.95 LPDDR4


# ------ Connections --------------------------------- #
connect "${cpu_instance}.emif0_ch0_axi emif_hps.s0_axi4"
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112 changes: 52 additions & 60 deletions sm_soc_devkit_ghrd/board/board_crv_pin_assignment_table.tcl
View file
Expand Up @@ -246,64 +246,56 @@ puts "Number of ports: [dict size $pin_assignment_table]"

set emif_name "emif_hps"
set pin_matrix [ list \
[ list "NAME" "MEM" "LOC" "x16_r1" "x24_r1" "x32_r1" "x40_r1" "x64_r1" "x72_r1" ] \
[ list "${emif_name}_emif_ref_clk_0_clk" "lpddr4" "PIN_BW78" "PIN_BW78" "PIN_BW78" "PIN_BW78" "PIN_BW78" "PIN_BW78" "PIN_BW78" ] \
[ list "${emif_name}_emif_oct_0_oct_rzqin" "lpddr4" "PIN_BH89" "PIN_BH89" "PIN_BH89" "PIN_BH89" "PIN_BH89" "PIN_BH89" "PIN_BH89" ] \
[ list "${emif_name}_emif_mem_0_mem_ck_t" "lpddr4" "PIN_BM81" "PIN_BM81" "PIN_BM81" "PIN_BM81" "PIN_BM81" "PIN_BM81" "PIN_BM81" ] \
[ list "${emif_name}_emif_mem_0_mem_ck_c" "lpddr4" "PIN_BP81" "PIN_BP81" "PIN_BP81" "PIN_BP81" "PIN_BP81" "PIN_BP81" "PIN_BP81" ] \
[ list "${emif_name}_emif_mem_0_mem_cke" "lpddr4" "PIN_BR81" "PIN_BR81" "PIN_BR81" "PIN_BR81" "PIN_BR81" "PIN_BR81" "PIN_BR81" ] \
[ list "${emif_name}_emif_mem_0_mem_cs" "lpddr4" "PIN_BR78" "PIN_BR78" "PIN_BR78" "PIN_BR78" "PIN_BR78" "PIN_BR78" "PIN_BR78" ] \
[ list "${emif_name}_emif_mem_0_mem_reset_n" "lpddr4" "PIN_BH92" "PIN_BH92" "PIN_BH92" "PIN_BH92" "PIN_BH92" "PIN_BH92" "PIN_BH92" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_t[0]" "lpddr4" "PIN_CH69" "PIN_CH69" "PIN_CH69" "PIN_CH69" "PIN_CH69" "PIN_CH69" "PIN_CH69" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_t[1]" "lpddr4" "PIN_BW69" "PIN_BW69" "PIN_BW69" "PIN_BW69" "PIN_BW69" "PIN_BW69" "PIN_BW69" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_t[2]" "lpddr4" "PIN_CH89" "PIN_CH89" "PIN_CH89" "PIN_CH89" "PIN_CH89" "PIN_CH89" "PIN_CH89" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_t[3]" "lpddr4" "PIN_CL88" "PIN_CL88" "PIN_CL88" "PIN_CL88" "PIN_CL88" "PIN_CL88" "PIN_CL88" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_t[4]" "lpddr4" unused unused unused unused unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_c[0]" "lpddr4" "PIN_CF69" "PIN_CF69" "PIN_CF69" "PIN_CF69" "PIN_CF69" "PIN_CF69" "PIN_CF69" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_c[1]" "lpddr4" "PIN_CA69" "PIN_CA69" "PIN_CA69" "PIN_CA69" "PIN_CA69" "PIN_CA69" "PIN_CA69" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_c[2]" "lpddr4" "PIN_CF89" "PIN_CF89" "PIN_CF89" "PIN_CF89" "PIN_CF89" "PIN_CF89" "PIN_CF89" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_c[3]" "lpddr4" "PIN_CK88" "PIN_CK88" "PIN_CK88" "PIN_CK88" "PIN_CK88" "PIN_CK88" "PIN_CK88" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_c[4]" "lpddr4" unused unused unused unused unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[0]" "lpddr4" "PIN_CA71" "PIN_CA71" "PIN_CA71" "PIN_CA71" "PIN_CA71" "PIN_CA71" "PIN_CA71" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[1]" "lpddr4" "PIN_CC71" "PIN_CC71" "PIN_CC71" "PIN_CC71" "PIN_CC71" "PIN_CC71" "PIN_CC71" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[2]" "lpddr4" "PIN_CH71" "PIN_CH71" "PIN_CH71" "PIN_CH71" "PIN_CH71" "PIN_CH71" "PIN_CH71" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[3]" "lpddr4" "PIN_CF71" "PIN_CF71" "PIN_CF71" "PIN_CF71" "PIN_CF71" "PIN_CF71" "PIN_CF71" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[4]" "lpddr4" "PIN_CH62" "PIN_CH62" "PIN_CH62" "PIN_CH62" "PIN_CH62" "PIN_CH62" "PIN_CH62" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[5]" "lpddr4" "PIN_CF62" "PIN_CF62" "PIN_CF62" "PIN_CF62" "PIN_CF62" "PIN_CF62" "PIN_CF62" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[6]" "lpddr4" "PIN_CH59" "PIN_CH59" "PIN_CH59" "PIN_CH59" "PIN_CH59" "PIN_CH59" "PIN_CH59" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[7]" "lpddr4" "PIN_CF59" "PIN_CF59" "PIN_CF59" "PIN_CF59" "PIN_CF59" "PIN_CF59" "PIN_CF59" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[8]" "lpddr4" "PIN_BR59" "PIN_BR59" "PIN_BR59" "PIN_BR59" "PIN_BR59" "PIN_BR59" "PIN_BR59" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[9]" "lpddr4" "PIN_BU59" "PIN_BU59" "PIN_BU59" "PIN_BU59" "PIN_BU59" "PIN_BU59" "PIN_BU59" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[10]" "lpddr4" "PIN_BW59" "PIN_BW59" "PIN_BW59" "PIN_BW59" "PIN_BW59" "PIN_BW59" "PIN_BW59" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[11]" "lpddr4" "PIN_CA59" "PIN_CA59" "PIN_CA59" "PIN_CA59" "PIN_CA59" "PIN_CA59" "PIN_CA59" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[12]" "lpddr4" "PIN_BU71" "PIN_BU71" "PIN_BU71" "PIN_BU71" "PIN_BU71" "PIN_BU71" "PIN_BU71" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[13]" "lpddr4" "PIN_BU69" "PIN_BU69" "PIN_BU69" "PIN_BU69" "PIN_BU69" "PIN_BU69" "PIN_BU69" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[14]" "lpddr4" "PIN_BR71" "PIN_BR71" "PIN_BR71" "PIN_BR71" "PIN_BR71" "PIN_BR71" "PIN_BR71" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[15]" "lpddr4" "PIN_BR69" "PIN_BR69" "PIN_BR69" "PIN_BR69" "PIN_BR69" "PIN_BR69" "PIN_BR69" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[16]" "lpddr4" "PIN_CC92" "PIN_CC92" "PIN_CC92" "PIN_CC92" "PIN_CC92" "PIN_CC92" "PIN_CC92" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[17]" "lpddr4" "PIN_CF92" "PIN_CF92" "PIN_CF92" "PIN_CF92" "PIN_CF92" "PIN_CF92" "PIN_CF92" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[18]" "lpddr4" "PIN_CA92" "PIN_CA92" "PIN_CA92" "PIN_CA92" "PIN_CA92" "PIN_CA92" "PIN_CA92" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[19]" "lpddr4" "PIN_CH92" "PIN_CH92" "PIN_CH92" "PIN_CH92" "PIN_CH92" "PIN_CH92" "PIN_CH92" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[20]" "lpddr4" "PIN_CC81" "PIN_CC81" "PIN_CC81" "PIN_CC81" "PIN_CC81" "PIN_CC81" "PIN_CC81" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[21]" "lpddr4" "PIN_CF78" "PIN_CF78" "PIN_CF78" "PIN_CF78" "PIN_CF78" "PIN_CF78" "PIN_CF78" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[22]" "lpddr4" "PIN_CH78" "PIN_CH78" "PIN_CH78" "PIN_CH78" "PIN_CH78" "PIN_CH78" "PIN_CH78" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[23]" "lpddr4" "PIN_CA81" "PIN_CA81" "PIN_CA81" "PIN_CA81" "PIN_CA81" "PIN_CA81" "PIN_CA81" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[24]" "lpddr4" "PIN_CL82" "PIN_CL82" "PIN_CL82" "PIN_CL82" "PIN_CL82" "PIN_CL82" "PIN_CL82" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[25]" "lpddr4" "PIN_CK80" "PIN_CK80" "PIN_CK80" "PIN_CK80" "PIN_CK80" "PIN_CK80" "PIN_CK80" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[26]" "lpddr4" "PIN_CK76" "PIN_CK76" "PIN_CK76" "PIN_CK76" "PIN_CK76" "PIN_CK76" "PIN_CK76" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[27]" "lpddr4" "PIN_CL76" "PIN_CL76" "PIN_CL76" "PIN_CL76" "PIN_CL76" "PIN_CL76" "PIN_CL76" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[28]" "lpddr4" "PIN_CK97" "PIN_CK97" "PIN_CK97" "PIN_CK97" "PIN_CK97" "PIN_CK97" "PIN_CK97" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[29]" "lpddr4" "PIN_CL97" "PIN_CL97" "PIN_CL97" "PIN_CL97" "PIN_CL97" "PIN_CL97" "PIN_CL97" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[30]" "lpddr4" "PIN_CK94" "PIN_CK94" "PIN_CK94" "PIN_CK94" "PIN_CK94" "PIN_CK94" "PIN_CK94" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[31]" "lpddr4" "PIN_CL91" "PIN_CL91" "PIN_CL91" "PIN_CL91" "PIN_CL91" "PIN_CL91" "PIN_CL91" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[0]" "lpddr4" "PIN_BR89" "PIN_BR89" "PIN_BR89" "PIN_BR89" "PIN_BR89" "PIN_BR89" "PIN_BR89" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[1]" "lpddr4" "PIN_BU89" "PIN_BU89" "PIN_BU89" "PIN_BU89" "PIN_BU89" "PIN_BU89" "PIN_BU89" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[2]" "lpddr4" "PIN_BR92" "PIN_BR92" "PIN_BR92" "PIN_BR92" "PIN_BR92" "PIN_BR92" "PIN_BR92" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[3]" "lpddr4" "PIN_BU92" "PIN_BU92" "PIN_BU92" "PIN_BU92" "PIN_BU92" "PIN_BU92" "PIN_BU92" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[4]" "lpddr4" "PIN_BW89" "PIN_BW89" "PIN_BW89" "PIN_BW89" "PIN_BW89" "PIN_BW89" "PIN_BW89" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[5]" "lpddr4" "PIN_CA89" "PIN_CA89" "PIN_CA89" "PIN_CA89" "PIN_CA89" "PIN_CA89" "PIN_CA89" ] \
[ list "${emif_name}_emif_mem_0_mem_dmi[0]" "lpddr4" "PIN_CA62" "PIN_CA62" "PIN_CA62" "PIN_CA62" "PIN_CA62" "PIN_CA62" "PIN_CA62" ] \
[ list "${emif_name}_emif_mem_0_mem_dmi[1]" "lpddr4" "PIN_BU62" "PIN_BU62" "PIN_BU62" "PIN_BU62" "PIN_BU62" "PIN_BU62" "PIN_BU62" ] \
[ list "${emif_name}_emif_mem_0_mem_dmi[2]" "lpddr4" "PIN_CF81" "PIN_CF81" "PIN_CF81" "PIN_CF81" "PIN_CF81" "PIN_CF81" "PIN_CF81" ] \
[ list "${emif_name}_emif_mem_0_mem_dmi[3]" "lpddr4" "PIN_CK85" "PIN_CK85" "PIN_CK85" "PIN_CK85" "PIN_CK85" "PIN_CK85" "PIN_CK85" ] \
[ list "NAME" "MEM" "LOC" "x16_r1" "x32_r1" ] \
[ list "${emif_name}_emif_ref_clk_0_clk" "lpddr4" "PIN_BW78" "PIN_BW78" "PIN_M105" ] \
[ list "${emif_name}_emif_oct_0_oct_rzqin" "lpddr4" "PIN_BH89" "PIN_BH89" "PIN_AK111" ] \
[ list "${emif_name}_emif_mem_0_mem_ck_t" "lpddr4" "PIN_BM81" "PIN_BM81" "PIN_AK107" ] \
[ list "${emif_name}_emif_mem_0_mem_ck_c" "lpddr4" "PIN_BP81" "PIN_BP81" "PIN_AK104" ] \
[ list "${emif_name}_emif_mem_0_mem_cke" "lpddr4" "PIN_BR81" "PIN_BR81" "PIN_V108" ] \
[ list "${emif_name}_emif_mem_0_mem_cs" "lpddr4" "PIN_BR78" "PIN_BR78" "PIN_T105" ] \
[ list "${emif_name}_emif_mem_0_mem_reset_n" "lpddr4" "PIN_BH92" "PIN_BH92" "PIN_AG111" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_t[0]" "lpddr4" "PIN_CH69" "PIN_CH69" "PIN_B122" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_t[1]" "lpddr4" "PIN_BW69" "PIN_BW69" "PIN_F114" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_c[0]" "lpddr4" "PIN_CF69" "PIN_CF69" "PIN_A125" ] \
[ list "${emif_name}_emif_mem_0_mem_dqs_c[1]" "lpddr4" "PIN_CA69" "PIN_CA69" "PIN_D114" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[0]" "lpddr4" "PIN_BR89" "PIN_BR89" "PIN_T114" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[1]" "lpddr4" "PIN_BU89" "PIN_BU89" "PIN_P114" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[2]" "lpddr4" "PIN_BR92" "PIN_BR92" "PIN_V117" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[3]" "lpddr4" "PIN_BU92" "PIN_BU92" "PIN_T117" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[4]" "lpddr4" "PIN_BW89" "PIN_BW89" "PIN_M114" ] \
[ list "${emif_name}_emif_mem_0_mem_ca[5]" "lpddr4" "PIN_CA89" "PIN_CA89" "PIN_K114" ] \
[ list "${emif_name}_emif_mem_0_mem_dmi[0]" "lpddr4" "PIN_CA62" "PIN_CA62" "PIN_B119" ] \
[ list "${emif_name}_emif_mem_0_mem_dmi[1]" "lpddr4" "PIN_BU62" "PIN_BU62" "PIN_F105" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[0]" "lpddr4" "PIN_CA71" "PIN_CA71" "PIN_B128" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[1]" "lpddr4" "PIN_CC71" "PIN_CC71" "PIN_A128" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[2]" "lpddr4" "PIN_CH71" "PIN_CH71" "PIN_B130" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[3]" "lpddr4" "PIN_CF71" "PIN_CF71" "PIN_A130" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[4]" "lpddr4" "PIN_CH62" "PIN_CH62" "PIN_B116" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[5]" "lpddr4" "PIN_CF62" "PIN_CF62" "PIN_A116" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[6]" "lpddr4" "PIN_CH59" "PIN_CH59" "PIN_B113" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[7]" "lpddr4" "PIN_CF59" "PIN_CF59" "PIN_A113" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[8]" "lpddr4" "PIN_BR59" "PIN_BR59" "PIN_F117" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[9]" "lpddr4" "PIN_BU59" "PIN_BU59" "PIN_H117" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[10]" "lpddr4" "PIN_BW59" "PIN_BW59" "PIN_K117" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[11]" "lpddr4" "PIN_CA59" "PIN_CA59" "PIN_M117" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[12]" "lpddr4" "PIN_BU71" "PIN_BU71" "PIN_H108" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[13]" "lpddr4" "PIN_BU69" "PIN_BU69" "PIN_F108" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[14]" "lpddr4" "PIN_BR71" "PIN_BR71" "PIN_M108" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[15]" "lpddr4" "PIN_BR69" "PIN_BR69" "PIN_K108" ] \
[ list "${emif_name}_emif_mem_0_mem_dq[16]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[17]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[18]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[19]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[20]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[21]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[22]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[23]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[24]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[25]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[26]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[27]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[28]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[29]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[30]" "lpddr4" unused unused unused ] \
[ list "${emif_name}_emif_mem_0_mem_dq[31]" "lpddr4" unused unused unused ] \
]

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