HSD#14021577699: dts: agilex5: update dmac data width param

Update dmac controller data width param to 3. Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@intel.com>
altera-opensource · Mar 21, 2024 · a04f992 · a04f992
1 parent b60da37
commit a04f992
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -763,7 +763,7 @@
 			#dma-cells = <1>;
 			dma-channels = <4>;
 			snps,dma-masters = <1>;
-			snps,data-width = <2>;
+			snps,data-width = <3>;
 			snps,block-size = <32767 32767 32767 32767>;
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
@@ -783,7 +783,7 @@
 			#dma-cells = <1>;
 			dma-channels = <4>;
 			snps,dma-masters = <1>;
-			snps,data-width = <2>;
+			snps,data-width = <3>;
 			snps,block-size = <32767 32767 32767 32767>;
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;