Add chandalar and quickfeather boards

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

nmigen_boards/quickfeather.py

@@ -0,0 +1,107 @@
+import os
+import subprocess
+
+from nmigen.build import *
+from nmigen.vendor.quicklogic import *
+from nmigen_boards.resources import *
+
+
+__all__ = ["QuickfeatherPlatform"]
+
+
+class QuickfeatherPlatform(QuicklogicPlatform):
+    device      = "ql-eos-s3_wlcsp"
+    part        = "PU64"
+    default_clk = "clk"
+    default_rst = None
+    speed = None
+    connectors = []
+    resources   = [
+        Resource("clk", 0, Pins("63", dir="i"), Clock(10e6), Attrs(IOSTANDARD="LVCMOS33")),
+
+        *ButtonResources(pins="62", attrs=Attrs(IOSTANDARD="LVCMOS33")),
+
+        RGBLEDResource(0, r="34", g="39", b="38", attrs=Attrs(IOSTANDARD="LVCMOS33")),
+
+        UARTResource(0,
+            rx="9", tx="8",
+            attrs=Attrs(IOSTANDARD="LVCMOS33")
+        ),
+
+        Resource("spi_master", 0,
+            Subsignal("clk", Pins("20", dir="i")),
+            Subsignal("miso", Pins("17", dir="o")),
+            Subsignal("mosi", Pins("16", dir="i")),
+            Subsignal("ss", Pins("11", dir="i")),
+            Subsignal("cs2", Pins("28", dir="i")),
+            Subsignal("cs3", Pins("18", dir="i")),
+            Attrs(IOSTANDARD="LVCMOS33")
+        ),
+
+        Resource("spi_slave", 0,
+            Subsignal("clk", Pins("40", dir="i")),
+            Subsignal("miso", Pins("42", dir="o")),
+            Subsignal("mosi", Pins("36", dir="i")),
+            Subsignal("cs_n", Pins("37", dir="i")),
+            Attrs(IOSTANDARD="LVCMOS33")
+        ),
+
+        Resource("i2c", 0,
+            Subsignal("scl", Pins("4", dir="o")),
+            Subsignal("sda", Pins("5", dir="o")),
+            Attrs(IOSTANDARD="LVCMOS33")
+        ),
+        Resource("i2c", 1,
+            Subsignal("scl", Pins("22", dir="o")),
+            Subsignal("sda", Pins("21", dir="o")),
+            Attrs(IOSTANDARD="LVCMOS33")
+        ),
+        DirectUSBResource(0, d_p="10", d_n="14",
+                attrs=Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("swd", 0,
+            Subsignal("clk", Pins("54", dir="io")),
+            Subsignal("io",  Pins("53", dir="io")),
+            Attrs(IOSTANDARD="LVCMOS33")
+        ),
+        Resource("io", 0, Pins("6", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("io", 1, Pins("3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("io", 2, Pins("64", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("io", 3, Pins("57", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("io", 4, Pins("56", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("io", 5, Pins("55", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("io", 6, Pins("59", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("io", 7, Pins("60", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+        Resource("io", 8, Pins("61", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
+    ]
+
+    def toolchain_prepare(self, fragment, name, **kwargs):
+        overrides = {}
+        return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
+
+    # This programmer requires OpenOCD with support for eos-s3:
+    # https://github.com/antmicro/openocd/tree/eos-s3-support
+    def toolchain_program(self, products, name):
+        openocd = os.environ.get("OPENOCD", "openocd")
+        gdb = os.environ.get("GDB", "gdb")
+        with products.extract("{}.bit".format(name)) as bitstream_filename:
+            bitstream_folder = os.path.dirname(bitstream_file)
+            top_path = bitstream_folder + "/top.cfg"
+            subprocess.call(["python", "-m", "quicklogic_fasm.bitstream_to_openocd", bitstream_file, top_path])
+            try:
+                openocd_proc = subprocess.Popen(["openocd", "-s", "tcl",
+                                                 "-f", "interface/ftdi/antmicro-ftdi-adapter.cfg",
+                                                 "-f", "interface/ftdi/swd-resistor-hack.cfg",
+                                                 "-f", "board/quicklogic_quickfeather.cfg",
+                                                 "-f", top_path])
+                gdb_commands = ["tar rem :3333", "monitor reset halt", "monitor load_bitstream"]
+                gdb_output_path = bitstream_folder + "/gdb.commands"
+                with open(gdb_output_path, 'w') as f:
+                    f.write("\n".join(gdb_commands))
+                subprocess.call([gdb, "-x", gdb_output_path])
+            except Exception as e:
+                openocd_proc.kill()
+                raise e
+
+if __name__ == "__main__":
+    from .test.blinky import *
+    QuickfeatherPlatform(toolchain="Quicklogic").build(Blinky(), do_program=False)