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It sounds like it is only possible to access Memory data with square-bracket array syntax (memory[ index ]) during simulation.
But when I try to build a bitstream from a design which uses that syntax, it seems to cause an infinite loop in nMigen instead of printing an error. Interrupting the process results in some nested LegalizeValue exceptions which eventually point to:
It sounds like this can be fixed by using the Memory object's read/write ports like the examples/basic/mem.py file demonstrates, but an error message might help make that more discoverable. Thanks!
The text was updated successfully, but these errors were encountered:
It sounds like it is only possible to access Memory data with square-bracket array syntax (
memory[ index ]
) during simulation.But when I try to build a bitstream from a design which uses that syntax, it seems to cause an infinite loop in nMigen instead of printing an error. Interrupting the process results in some nested
LegalizeValue
exceptions which eventually point to:It sounds like this can be fixed by using the Memory object's read/write ports like the
examples/basic/mem.py
file demonstrates, but an error message might help make that more discoverable. Thanks!The text was updated successfully, but these errors were encountered: