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GlasgowEmbedded/glasgow
GlasgowEmbedded/glasgow PublicScots Army Knife for electronics
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amaranth-lang/amaranth
amaranth-lang/amaranth PublicA modern hardware definition language and toolchain based on Python
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llvm/llvm-project
llvm/llvm-project PublicThe LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
2,379 contributions in the last year
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Contribution activity
February 2024
Created 81 commits in 13 repositories
Created a pull request in YosysHQ/yosys that received 6 comments
read_verilog: correctly format hdlname attribute value
The leading slash is not a part of the attribute as it only concerns public values. No idea why this fails tests. @povik, do you know?
+2
−2
lines changed
•
6
comments
Opened 25 other pull requests in 4 repositories
amaranth-lang/amaranth
18
merged
1
open
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Fix link rot in docs
This contribution was made on Feb 15
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Remember origins of a fragment during elaboration
This contribution was made on Feb 13
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Update README
This contribution was made on Feb 13
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CI: publish packages automatically
This contribution was made on Feb 13
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docs: use
:py:role for inline Python code, not:pc:. NFCThis contribution was made on Feb 13 -
Add full support for running Amaranth on Pyodide [0.4 backport]
This contribution was made on Feb 13
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Add full support for running Amaranth on Pyodide
This contribution was made on Feb 13
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Require Yosys 0.38 [0.4 backport]
This contribution was made on Feb 13
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Require Yosys 0.38
This contribution was made on Feb 13
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Minor documentation fixes
This contribution was made on Feb 13
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Add reference documentation for
Value,ValueCastable,ValueLikeThis contribution was made on Feb 13 -
Remove
ValueKey,ValueDict,ValueSetThis contribution was made on Feb 11 -
Fix toolchain environment variable check, attempt #2
This contribution was made on Feb 11
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New intermediate representation
This contribution was made on Feb 11
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CI: Update actions to Node 20
This contribution was made on Feb 9
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Track member source locations in
lib.wiringThis contribution was made on Feb 8 -
Fix toolchain environment variable check
This contribution was made on Feb 8
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Remove features deprecated in past releases
This contribution was made on Feb 6
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Remove subclassing of
AnyValueandPropertyThis contribution was made on Feb 5
YosysHQ/yosys
1
open
3
merged
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cxxrtl: expose scope information in the C++ API
This contribution was made on Feb 13
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cxxrtl: misc improvements
This contribution was made on Feb 13
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cxxrtl: fix debug information for zero-width items
This contribution was made on Feb 13
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read_verilog: don't include empty
opt_sva_labelin spanThis contribution was made on Feb 8
amaranth-lang/rfcs
1
merged
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RFC #27: Amend to deprecate
add_sync_processrather thanadd_processThis contribution was made on Feb 8
GlasgowEmbedded/glasgow
1
merged
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Update
pdm.min.lockThis contribution was made on Feb 3
Reviewed 43 pull requests in 6 repositories
amaranth-lang/amaranth
25 pull requests
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hdl._ast: make
Shapeimmutable and hashable.This contribution was made on Feb 16 -
Implement RFC 43: Rename
reset=toinit=.This contribution was made on Feb 15 -
ir: kill Fragment.ports
This contribution was made on Feb 15
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hdl._dsl: fix using 0-width
Switchwith integer keys. [0.4 backport]This contribution was made on Feb 14 -
hdl._ast: fix using 0-width
Switchwith integer keys. [0.4 backport]This contribution was made on Feb 14 -
hdl._ast: fix using 0-width
Switchwith integer keys.This contribution was made on Feb 14 -
sim: fix using 0-width
Switch.This contribution was made on Feb 14 -
pyproject: change yosys-yowasp requirement to match RTLIL backend.
This contribution was made on Feb 14
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sim: fix using 0-width
Switch. [0.4 backport]This contribution was made on Feb 14 -
hdl._dsl: fix using 0-width
Switchwith integer keys.This contribution was made on Feb 14 -
README: add the full list of supported AMD devices.
This contribution was made on Feb 13
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docs: remove leftover TODO and warning from #1003.
This contribution was made on Feb 13
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vendor._intel: use
dffinstead of$dff.This contribution was made on Feb 13 -
vendor.lattice_ice40: use
SB_DFFinstead of$dff.This contribution was made on Feb 13 -
Minor documentation fixes
This contribution was made on Feb 13
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hdl.ast: fix
shift_rightandas_signededge cases. [0.4 backport]This contribution was made on Feb 13 -
hdl._ast: fix
shift_rightandas_signededge cases.This contribution was made on Feb 13 -
hdl._ast: deprecate
ValueCastable.lowermethod.This contribution was made on Feb 13 -
Add reference documentation for
Value,ValueCastable,ValueLikeThis contribution was made on Feb 13 -
hdl._nir: implement __repr__ on NIR classes.
This contribution was made on Feb 13
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Implement RFC 27 amendment: deprecate
add_sync_process, notadd_process.This contribution was made on Feb 12 -
tests: stop using implicit ports.
This contribution was made on Feb 12
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hdl._nir: fix docstring typos.
This contribution was made on Feb 11
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sim: prefix fields with
\.This contribution was made on Feb 9 -
hdl: consistently use "comb" for combinatorial domain.
This contribution was made on Feb 9
- Some pull request reviews not shown.
GlasgowEmbedded/glasgow
4 pull requests
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software: remove uses of the deprecated
fwftparameter.This contribution was made on Feb 14 -
applet.interface.jtag_svf: fix
STATE RESET.This contribution was made on Feb 7 -
applet.interface.jtag_probe: add support for shifting 0 bits.
This contribution was made on Feb 7
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software: Update multidict to 6.0.5 to fix Python 3.13 build
This contribution was made on Feb 1
YosysHQ/yosys
3 pull requests
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tests/various/clk2fflogic_effects.sh: fix on macOS
This contribution was made on Feb 10
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opt_lut: Remove leftover
-dlogichelpThis contribution was made on Feb 8 -
Follow the XDG Base Directory Specification
This contribution was made on Feb 1
conda-forge/amaranth-feedstock
1 pull request
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amaranth v0.4.2
This contribution was made on Feb 16
kuznia-rdzeni/coreblocks
1 pull request
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A step towards amaranth
v0.5.0This contribution was made on Feb 11
amaranth-lang/amaranth-soc
1 pull request
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Implement RFC 16 (CSR register API)
This contribution was made on Feb 8
Created an issue in bytecodealliance/jco that received 2 comments
--instantiation sync seems broken
jco 1.0.0 generates this code for --instantiate sync:
export function instantiate(getCoreModule, imports, instantiateCore = WebAssembly.Instance) {
T…
2
comments
Opened 15 other issues in 2 repositories
amaranth-lang/amaranth
8
open
6
closed
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Structured source locations
This contribution was made on Feb 13
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Attach
srcattributes to emittedmodules andcellsThis contribution was made on Feb 13 -
Make
Shapeimmutable and hashableThis contribution was made on Feb 13 -
Deprecate and remove
ValueCastable.lowermethodThis contribution was made on Feb 13 -
Tracking issue for RFC 43: Rename
reset=toinit=This contribution was made on Feb 12 -
PySim VCDWriter is useless with
io.StringIOThis contribution was made on Feb 11 -
Tracer should probably ignore a single leading
_in namesThis contribution was made on Feb 11 -
Refactor
back.rtlilto convert Amaranth IR structures to Yosys IR structuresThis contribution was made on Feb 10 -
Consistently use "comb" for combinatorial domain instead of sometimes "comb" and sometimes None
This contribution was made on Feb 9
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Source locations for component members created from annotations are wrong
This contribution was made on Feb 6
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Tracking issue for RFC 42:
Constfrom shape-castableThis contribution was made on Feb 5 -
Tracking issue for RFC 45: Move
hdl.Memorytolib.MemoryThis contribution was made on Feb 5 -
Tracking issue for RFC 27: Testbench functions for the simulator
This contribution was made on Feb 5
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Refactor
Fragmentto have a mapping from statements to domainsThis contribution was made on Feb 5
bytecodealliance/jco
1
open
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Selecting instantiation mode at compile time is limiting
This contribution was made on Feb 13
79
contributions
in private repositories
Feb 5 – Feb 16