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The following code does not complete (at least not in 1 minute, so I call it infinite ;) )
from nmigen import *
from nmigen.sim import *
def elaborate(self, _):
m = Module()
a = Signal(32)
b = Signal(32)
z = Signal(32)
m.d.comb += z.eq(a << b)
m = Module()
m.submodules.a = A()
sim = Simulator(m)
The problem seems to be the a << b operation.
a << b
The text was updated successfully, but these errors were encountered:
@hellow554 It is simply very slow, as a << b generates a 4294967327 bit wide intermediate wire. Converting this to verilog / rtlil already catches this.
Maybe a similar check should be added to the simulator backend.
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And a right shift is okay, because there are only 32 possible values?
So the solution would be to shorten b to e.g. 5 bits?
Yep, the manual has this note. We could probably add a similar check to pysim as to the RTLIL backend.
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