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Left shift + simulator = infinite (?) loop #588

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hellow554 opened this issue Feb 2, 2021 · 4 comments
Closed

Left shift + simulator = infinite (?) loop #588

hellow554 opened this issue Feb 2, 2021 · 4 comments

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@hellow554
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hellow554 commented Feb 2, 2021

The following code does not complete (at least not in 1 minute, so I call it infinite ;) )

from nmigen import *
from nmigen.sim import *

class A(Elaboratable):
    def elaborate(self, _):
        m = Module()
        a = Signal(32)
        b = Signal(32)
        z = Signal(32)
        m.d.comb += z.eq(a << b)
        return m

m = Module()
m.submodules.a = A()
sim = Simulator(m)

The problem seems to be the a << b operation.

@rroohhh
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rroohhh commented Feb 2, 2021

@hellow554 It is simply very slow, as a << b generates a 4294967327 bit wide intermediate wire. Converting this to verilog / rtlil already catches this.

Maybe a similar check should be added to the simulator backend.

@hellow554
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hellow554 commented Feb 2, 2021

And a right shift is okay, because there are only 32 possible values?
So the solution would be to shorten b to e.g. 5 bits?

@rroohhh
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rroohhh commented Feb 2, 2021

Yep

@whitequark
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whitequark commented Feb 2, 2021

Yep, the manual has this note. We could probably add a similar check to pysim as to the RTLIL backend.

@whitequark whitequark added this to the 0.3 milestone Dec 11, 2021
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