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mtd: spi-nor: core: Couple the number of address bytes with the addre…
…ss mode Some of Infineon chips support volatile version of configuration registers and it is recommended to update volatile registers in the field application due to a risk of the non-volatile registers corruption by power interrupt. Such a volatile configuration register is used to enable the Quad mode. The register write sequence requires the number of bytes of address in order to be programmed. As it was before, the nor->addr_width was set to 4 before calling the volatile Quad enable method. This was incorrect as the address mode was still at default (3-byte address), which resulted in incorrect register configuration. Move the setting of the number of bytes of adress after the the Quad enable method to allow reads or writes to registers that reguire the number of address bytes to work with the default address mode. Now the number of address bytes and the adress mode are tightly coupled, which is a natural change. Other (standard) Quad Enable methods are not affected, as they don't require the number of address bytes, so no functionality changes expected. Reported-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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