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1. riscv-multi-core-lotr riscv-multi-core-lotr Public

   RISCV core RV32I/E.4 threads in a ring architecture

   SystemVerilog 27 7

2. rvc_asap rvc_asap Public

   riscv-core-as-simple-as-passible

   SystemVerilog 9 3

3. FPGA-MAFIA/fpga_mafia FPGA-MAFIA/fpga_mafia Public

   Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.

   SystemVerilog 9 4

4. abd_dino_game abd_dino_game Public

   Testing the dino game in python so i can train a NN to and get the weights & biases for my RISCV C program.

   Python