80211.a-wireless-local-network

• Phase 1: developed Scrambler and Descrambler in Verilog and Matlab and verified the design using a test bench provided by myself.

• Phase 2: developed Encoder and Decoder ( Viterbi algorithm ) in Verilog and Matlab and verified the design using a test bench.

• Phase 3: developed Interleaver and Deinterleaver in Verilog and Matlab and verified the design using a test bench.

• Phase 4: Combining these three Modules, We could finally test the transmitter as well as the receiver using another test bench.