Design-mips-processor

This project designs a mips processor in two methods, single cycle and pipeline based on verilog HDL language.

Phase1 : Implement mode element modules for CPU design

in this phase I implement Instruction and Data memory, Register file and ALU.

Phase2 : Implement single cycle processor based on mips instructions using Phase1 elements

Phase3 : Implement Pipeline processor based on mips instructions using Phase1 elements

Phase4 : Implement cache memory