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ad4630.c
1648 lines (1393 loc) · 42 KB
/
ad4630.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD4630 SPI ADC driver
*
* Copyright 2022 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dmaengine.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/buffer-dma.h>
#include <linux/iio/buffer-dmaengine.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/limits.h>
#include <linux/kconfig.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-engine-ex.h>
#include <linux/util_macros.h>
#include <linux/units.h>
#include <linux/types.h>
#define AD4630_REG_INTERFACE_CONFIG_A 0x00
#define AD4630_REG_INTERFACE_CONFIG_B 0x01
#define AD4630_REG_DEVICE_CONFIG 0x02
#define AD4630_REG_CHIP_TYPE 0x03
#define AD4630_REG_PRODUCT_ID_L 0x04
#define AD4630_REG_PRODUCT_ID_H 0x05
#define AD4630_REG_CHIP_GRADE 0x06
#define AD4630_REG_SCRATCH_PAD 0x0A
#define AD4630_REG_SPI_REVISION 0x0B
#define AD4630_REG_VENDOR_L 0x0C
#define AD4630_REG_VENDOR_H 0x0D
#define AD4630_REG_STREAM_MODE 0x0E
#define AD4630_REG_EXIT_CFG_MODE 0x14
#define AD4630_REG_AVG 0x15
#define AD4630_REG_OFFSET_X0_0 0x16
#define AD4630_REG_OFFSET_X0_1 0x17
#define AD4630_REG_OFFSET_X0_2 0x18
#define AD4630_REG_OFFSET_X1_0 0x19
#define AD4630_REG_OFFSET_X1_1 0x1A
#define AD4630_REG_OFFSET_X1_2 0x1B
#define AD4630_REG_GAIN_X0_LSB 0x1C
#define AD4630_REG_GAIN_X0_MSB 0x1D
#define AD4630_REG_GAIN_X1_LSB 0x1E
#define AD4630_REG_GAIN_X1_MSB 0x1F
#define AD4630_REG_MODES 0x20
#define AD4630_REG_OSCILATOR 0x21
#define AD4630_REG_IO 0x22
#define AD4630_REG_PAT0 0x23
#define AD4630_REG_PAT1 0x24
#define AD4630_REG_PAT2 0x25
#define AD4630_REG_PAT3 0x26
#define AD4630_REG_DIG_DIAG 0x34
#define AD4630_REG_DIG_ERR 0x35
/* INTERFACE_CONFIG_A */
#define AD4630_SW_RESET (BIT(0) | BIT(7))
/* CHIP GRADE */
#define AD4630_MSK_CHIP_GRADE GENMASK(7, 3)
#define AD4630_CHIP_GRADE(grade) FIELD_GET(AD4630_MSK_CHIP_GRADE, grade)
/* MODES */
#define AD4630_LANE_MODE_MSK GENMASK(7, 6)
#define AD4630_CLK_MODE_MSK GENMASK(5, 4)
#define AD4630_DATA_RATE_MODE_MSK BIT(3)
#define AD4630_OUT_DATA_MODE_MSK GENMASK(2, 0)
/* EXIT_CFG_MD */
#define AD4630_EXIT_CFG_MODE BIT(0)
/* AVG */
#define AD4630_AVG_FILTER_RESET BIT(7)
/* OFFSET */
#define AD4630_REG_CHAN_OFFSET(ch) (AD4630_REG_OFFSET_X0_2 + 3 * (ch))
/* HARDWARE_GAIN */
#define AD4630_REG_CHAN_GAIN(ch) (AD4630_REG_GAIN_X0_MSB + 2 * (ch))
#define AD4630_GAIN_MAX 1999970
#define ADAQ4224_GAIN_MAX_NANO 6670000000
/* POWER MODE*/
#define AD4630_POWER_MODE_MSK GENMASK(1, 0)
#define AD4630_LOW_POWER_MODE 3
/* SPI transfer */
#define AD4630_SPI_REG_ACCESS_SPEED 40000000UL
#define AD4630_SPI_SAMPLING_SPEED 80000000UL
/* sequence starting with "1 0 1" to enable reg access */
#define AD4630_REG_ACCESS 0x2000
/* Sampling timing */
#define AD4630_MAX_RATE_1_LANE 1750000
#define AD4630_MAX_RATE 2000000
#define AD4630_MAX_CHANNEL_NR 3
#define AD4630_VREF_MIN (4096 * MILLI)
#define AD4630_VREF_MAX (5000 * MILLI)
#define AD4630_CHAN_INFO_NONE 0
#define ADAQ4224_PGA_PINS 2
#define ADAQ4224_PGA_1_BITMAP 0
#define ADAQ4224_PGA_2_BITMAP BIT(0)
#define ADAQ4224_PGA_3_BITMAP BIT(1)
#define ADAQ4224_PGA_4_BITMAP GENMASK(1, 0)
enum {
AD4630_ONE_LANE_PER_CH,
AD4630_TWO_LANES_PER_CH,
AD4630_FOUR_LANES_PER_CH,
AD4630_SHARED_TWO_CH,
};
enum {
AD4630_16_DIFF = 0x00,
AD4630_24_DIFF = 0x00,
AD4630_16_DIFF_8_COM = 0x01,
AD4630_24_DIFF_8_COM = 0x02,
AD4630_30_AVERAGED_DIFF = 0x03,
AD4630_32_PATTERN = 0x04
};
enum {
AD4630_SPI_COMPATIBLE_MODE,
AD4630_ECHO_CLOCK_MODE,
AD4630_CLOCK_HOST_MODE,
};
enum {
ID_AD4030_24,
ID_AD4032_24,
ID_AD4630_16,
ID_AD4632_16,
ID_AD4630_24,
ID_AD4632_24,
ID_ADAQ4216,
ID_ADAQ4220,
ID_ADAQ4224,
};
enum {
AD4630_033_GAIN = 0,
AD4630_056_GAIN = 1,
AD4630_222_GAIN = 2,
AD4630_667_GAIN = 3,
AD4630_MAX_PGA,
};
/*
* Gains computed as fractions of 1000 so they can be expressed by integers.
*/
static const int ad4630_gains[4] = {
330, 560, 2220, 6670
};
/*
* Gains stored and computed as fractions to avoid introducing rounding erros.
*/
static const int ad4630_gains_frac[4][2] = {
[AD4630_033_GAIN] = { 1, 3 },
[AD4630_056_GAIN] = { 5, 9 },
[AD4630_222_GAIN] = { 20, 9 },
[AD4630_667_GAIN] = { 20, 3 },
};
struct ad4630_out_mode {
const struct iio_chan_spec channels[AD4630_MAX_CHANNEL_NR];
u32 data_width;
};
struct ad4630_chip_info {
const unsigned long *available_masks;
const struct ad4630_out_mode *modes;
const char *name;
unsigned long out_modes_mask;
int min_offset;
int max_offset;
u16 base_word_len;
u8 grade;
u8 n_channels;
bool has_pga;
};
struct ad4630_state {
const struct ad4630_chip_info *chip;
struct regulator_bulk_data regulators[3];
struct pwm_device *conv_trigger;
struct pwm_device *fetch_trigger;
struct gpio_descs *pga_gpios;
struct spi_device *spi;
struct regmap *regmap;
int vref;
int vio;
int pga_idx;
int scale_tbl[ARRAY_SIZE(ad4630_gains)][2];
unsigned int out_data;
unsigned int max_rate;
/* offload sampling spi message */
struct spi_transfer offload_xfer;
struct spi_message offload_msg;
bool use_spi_trigger;
u8 bits_per_word;
u8 pattern_bits_per_word;
u8 tx_data[6] __aligned(ARCH_KMALLOC_MINALIGN);
u8 rx_data[6];
};
static int ad4630_spi_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct ad4630_state *st = context;
struct spi_transfer xfer = {
.speed_hz = AD4630_SPI_REG_ACCESS_SPEED,
.tx_buf = st->tx_data,
.rx_buf = st->rx_data,
.len = reg_size + val_size,
};
int ret;
memcpy(st->tx_data, reg, reg_size);
ret = spi_sync_transfer(st->spi, &xfer, 1);
if (ret)
return ret;
memcpy(val, &st->rx_data[2], val_size);
return ret;
}
static int ad4630_spi_write(void *context, const void *data, size_t count)
{
const struct ad4630_state *st = context;
return spi_write(st->spi, data, count);
}
static int ad4630_reg_access(struct iio_dev *indio_dev, unsigned int reg,
unsigned int writeval, unsigned int *readval)
{
const struct ad4630_state *st = iio_priv(indio_dev);
if (readval)
return regmap_read(st->regmap, reg, readval);
return regmap_write(st->regmap, reg, writeval);
}
static void ad4630_get_sampling_freq(const struct ad4630_state *st, int *freq)
{
struct pwm_state conversion_state;
pwm_get_state(st->conv_trigger, &conversion_state);
*freq = DIV_ROUND_CLOSEST_ULL(PICO, conversion_state.period);
}
static int ad4630_get_chan_gain(struct iio_dev *indio_dev, int ch, int *val)
{
const struct ad4630_state *st = iio_priv(indio_dev);
__be16 gain;
int ret;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = regmap_bulk_read(st->regmap, AD4630_REG_CHAN_GAIN(ch), &gain, 2);
if (ret)
goto out_error;
*val = DIV_ROUND_CLOSEST_ULL(be16_to_cpu(gain) * 1000000ULL, 0x8000);
out_error:
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int ad4630_get_chan_offset(struct iio_dev *indio_dev, int ch, int *val)
{
const struct ad4630_state *st = iio_priv(indio_dev);
__be32 offset;
int ret;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = regmap_bulk_read(st->regmap, AD4630_REG_CHAN_OFFSET(ch),
&offset, 3);
if (ret)
goto out_error;
*val = be32_to_cpu(offset) >> 8;
/* For 16bit chips, the third byte is RESERVED. We can read it but it's a don't care...*/
if (st->chip->base_word_len == 16)
*val = *val >> 8;
*val = sign_extend32(*val, st->chip->base_word_len - 1);
out_error:
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int ad4630_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long info)
{
struct ad4630_state *st = iio_priv(indio_dev);
unsigned int temp;
int ret;
switch (info) {
case IIO_CHAN_INFO_SAMP_FREQ:
ad4630_get_sampling_freq(st, val);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (st->chip->has_pga) {
*val = st->scale_tbl[st->pga_idx][0];
*val2 = st->scale_tbl[st->pga_idx][1];
return IIO_VAL_INT_PLUS_NANO;
}
*val = (st->vref * 2) / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_CALIBSCALE:
ret = ad4630_get_chan_gain(indio_dev, chan->channel, &temp);
if (ret)
return ret;
*val = temp / 1000000;
*val2 = temp % 1000000;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_CALIBBIAS:
ret = ad4630_get_chan_offset(indio_dev, chan->channel, val);
if (ret)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ad4630_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long info)
{
struct ad4630_state *st = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_SCALE:
*vals = (int *)st->scale_tbl;
*length = ARRAY_SIZE(ad4630_gains) * 2;
*type = IIO_VAL_INT_PLUS_NANO;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int __ad4630_set_sampling_freq(const struct ad4630_state *st, unsigned int freq)
{
struct pwm_state conv_state = {
.duty_cycle = 10000,
.time_unit = PWM_UNIT_PSEC,
}, fetch_state = {
.duty_cycle = 10000,
.time_unit = PWM_UNIT_PSEC,
};
int ret;
conv_state.period = DIV_ROUND_CLOSEST_ULL(PICO, freq);
ret = pwm_apply_state(st->conv_trigger, &conv_state);
if (ret)
return ret;
if (!st->fetch_trigger)
return 0;
fetch_state.period = conv_state.period;
if (st->out_data == AD4630_30_AVERAGED_DIFF) {
u32 avg;
ret = regmap_read(st->regmap, AD4630_REG_AVG, &avg);
if (ret)
return ret;
fetch_state.period *= 1 << avg;
}
/*
* The hardware does the capture on zone 2 (when spi trigger PWM
* is used). This means that the spi trigger signal should happen at
* tsync + tquiet_con_delay being tsync the conversion signal period
* and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly.
*/
fetch_state.phase = fetch_state.period + 9800;
return pwm_apply_state(st->fetch_trigger, &fetch_state);
}
static int ad4630_set_sampling_freq(struct iio_dev *indio_dev, unsigned int freq)
{
const struct ad4630_state *st = iio_priv(indio_dev);
int ret;
if (!freq || freq > st->max_rate)
return -EINVAL;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = __ad4630_set_sampling_freq(st, freq);
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int ad4630_set_chan_offset(struct iio_dev *indio_dev, int ch, int offset)
{
const struct ad4630_state *st = iio_priv(indio_dev);
__be32 val;
int ret;
if (offset < st->chip->min_offset || offset > st->chip->max_offset)
return -EINVAL;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
if (st->chip->base_word_len == 16)
val = cpu_to_be32(offset << 16);
else
val = cpu_to_be32(offset << 8);
ret = regmap_bulk_write(st->regmap, AD4630_REG_CHAN_OFFSET(ch),
&val, 3);
iio_device_release_direct_mode(indio_dev);
return ret;
}
static void ad4630_fill_scale_tbl(struct ad4630_state *st)
{
int val, val2, tmp0, tmp1, i;
u64 tmp2;
val2 = st->chip->modes[st->out_data].channels->scan_type.realbits;
for (i = 0; i < ARRAY_SIZE(ad4630_gains); i++) {
val = (st->vref * 2) / 1000;
/* Multiply by MILLI here to avoid losing precision */
val = mult_frac(val, ad4630_gains_frac[i][1] * MILLI,
ad4630_gains_frac[i][0]);
/* Would multiply by NANO here but we already multiplied by MILLI */
tmp2 = shift_right((u64)val * MICRO, val2);
tmp0 = (int)div_s64_rem(tmp2, NANO, &tmp1);
st->scale_tbl[i][0] = tmp0; /* Integer part */
st->scale_tbl[i][1] = abs(tmp1); /* Fractional part */
}
}
static int ad4630_calc_pga_gain(int gain_int, int gain_fract, int vref,
int precision)
{
u64 gain_nano, tmp;
int gain_idx;
gain_nano = gain_int * NANO + gain_fract;
if (gain_nano < 0 || gain_nano > ADAQ4224_GAIN_MAX_NANO)
return -EINVAL;
tmp = DIV_ROUND_CLOSEST_ULL(gain_nano << precision, NANO);
gain_nano = DIV_ROUND_CLOSEST_ULL(vref * 2, tmp);
gain_idx = find_closest(gain_nano, ad4630_gains,
ARRAY_SIZE(ad4630_gains));
return gain_idx;
}
static int ad4630_set_pga_gain(struct iio_dev *indio_dev, int gain_idx)
{
struct ad4630_state *st = iio_priv(indio_dev);
DECLARE_BITMAP(values, ADAQ4224_PGA_PINS);
int ret;
/* Set appropriate status for A0, A1 pins according to requested gain */
switch (gain_idx) {
case 0:
values[0] = ADAQ4224_PGA_1_BITMAP;
break;
case 1:
values[0] = ADAQ4224_PGA_2_BITMAP;
break;
case 2:
values[0] = ADAQ4224_PGA_3_BITMAP;
break;
case 3:
values[0] = ADAQ4224_PGA_4_BITMAP;
break;
default:
return -EINVAL;
}
ret = gpiod_set_array_value_cansleep(ADAQ4224_PGA_PINS,
st->pga_gpios->desc,
st->pga_gpios->info, values);
if (!ret)
st->pga_idx = gain_idx;
return ret;
}
static int ad4630_set_chan_gain(struct iio_dev *indio_dev, int ch,
int gain_int, int gain_frac)
{
const struct ad4630_state *st = iio_priv(indio_dev);
__be16 val;
u64 gain;
int ret;
gain = gain_int * MICRO + gain_frac;
if (gain < 0 || gain > AD4630_GAIN_MAX)
return -EINVAL;
gain = DIV_ROUND_CLOSEST_ULL(gain * 0x8000, 1000000);
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
val = cpu_to_be16(gain);
ret = regmap_bulk_write(st->regmap, AD4630_REG_CHAN_GAIN(ch), &val, 2);
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int ad4630_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
default:
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int ad4630_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long info)
{
struct ad4630_state *st = iio_priv(indio_dev);
int gain_idx;
switch (info) {
case IIO_CHAN_INFO_SAMP_FREQ:
return ad4630_set_sampling_freq(indio_dev, val);
case IIO_CHAN_INFO_SCALE:
gain_idx = ad4630_calc_pga_gain(val, val2, st->vref,
chan->scan_type.realbits);
return ad4630_set_pga_gain(indio_dev, gain_idx);
case IIO_CHAN_INFO_CALIBSCALE:
return ad4630_set_chan_gain(indio_dev, chan->channel, val,
val2);
case IIO_CHAN_INFO_CALIBBIAS:
return ad4630_set_chan_offset(indio_dev, chan->channel, val);
default:
return -EINVAL;
}
}
static int ad4630_update_sample_fetch_trigger(const struct ad4630_state *st, u32 avg)
{
struct pwm_state fetch_state, conv_state;
if (!st->fetch_trigger)
return 0;
pwm_get_state(st->conv_trigger, &conv_state);
pwm_get_state(st->fetch_trigger, &fetch_state);
fetch_state.period = conv_state.period * 1 << avg;
fetch_state.phase = fetch_state.period + 9800;
return pwm_apply_state(st->fetch_trigger, &fetch_state);
}
static int ad4630_set_avg_frame_len(struct iio_dev *dev,
const struct iio_chan_spec *chan,
unsigned int avg_len)
{
const struct ad4630_state *st = iio_priv(dev);
int ret;
ret = iio_device_claim_direct_mode(dev);
if (ret)
return ret;
ret = regmap_write(st->regmap, AD4630_REG_AVG, avg_len + 1);
if (ret)
goto out_error;
ret = ad4630_update_sample_fetch_trigger(st, avg_len + 1);
out_error:
iio_device_release_direct_mode(dev);
return ret;
}
static int ad4630_get_avg_frame_len(struct iio_dev *dev,
const struct iio_chan_spec *chan)
{
const struct ad4630_state *st = iio_priv(dev);
unsigned int avg_len;
int ret;
ret = iio_device_claim_direct_mode(dev);
if (ret)
return ret;
ret = regmap_read(st->regmap, AD4630_REG_AVG, &avg_len);
iio_device_release_direct_mode(dev);
if (ret)
return ret;
return avg_len - 1;
}
static int ad4630_sampling_enable(const struct ad4630_state *st, bool enable)
{
struct pwm_state conv_state, fetch_state;
int ret;
pwm_get_state(st->conv_trigger, &conv_state);
conv_state.enabled = enable;
ret = pwm_apply_state(st->conv_trigger, &conv_state);
if (ret)
return ret;
if (!st->fetch_trigger)
return 0;
pwm_get_state(st->fetch_trigger, &fetch_state);
fetch_state.enabled = enable;
return pwm_apply_state(st->fetch_trigger, &fetch_state);
}
static int ad4630_spi_transfer_update(struct ad4630_state *st)
{
u8 bits_per_w;
u32 mode;
int ret;
ret = regmap_read(st->regmap, AD4630_REG_MODES, &mode);
if (ret)
return ret;
if (FIELD_GET(AD4630_OUT_DATA_MODE_MSK, mode) == AD4630_32_PATTERN) {
bits_per_w = st->pattern_bits_per_word;
/*
* If the previous mode is averaging, we need to update the
* fetch PWM signal as there's no averaging in the test pattern
* mode and the user might have already configured some
* averaging.
*/
if (st->out_data == AD4630_30_AVERAGED_DIFF)
ad4630_update_sample_fetch_trigger(st, 0);
} else {
bits_per_w = st->bits_per_word;
/* Restore the fetch PWM signal */
if (st->out_data == AD4630_30_AVERAGED_DIFF) {
u32 avg;
ret = regmap_read(st->regmap, AD4630_REG_AVG, &avg);
if (ret)
return ret;
ad4630_update_sample_fetch_trigger(st, avg);
}
}
st->offload_xfer.bits_per_word = bits_per_w;
return 0;
}
static int ad4630_buffer_preenable(struct iio_dev *indio_dev)
{
struct ad4630_state *st = iio_priv(indio_dev);
int ret;
ret = pm_runtime_resume_and_get(&st->spi->dev);
if (ret < 0)
return ret;
/* we might need to update the spi transfer if in test pattern mode */
ret = ad4630_spi_transfer_update(st);
if (ret)
goto out_error;
ret = regmap_write(st->regmap, AD4630_REG_EXIT_CFG_MODE, BIT(0));
if (ret)
goto out_error;
ret = spi_optimize_message(st->spi, &st->offload_msg);
if (ret < 0)
goto out_error;
spi_bus_lock(st->spi->master);
spi_engine_ex_offload_load_msg(st->spi, &st->offload_msg);
spi_engine_ex_offload_enable(st->spi, true);
ad4630_sampling_enable(st, true);
return 0;
out_error:
pm_runtime_mark_last_busy(&st->spi->dev);
pm_runtime_put_autosuspend(&st->spi->dev);
return ret;
}
static int ad4630_buffer_postdisable(struct iio_dev *indio_dev)
{
struct ad4630_state *st = iio_priv(indio_dev);
u32 dummy;
int ret;
ret = ad4630_sampling_enable(st, false);
if (ret)
goto out_error;
spi_engine_ex_offload_enable(st->spi, false);
spi_bus_unlock(st->spi->master);
spi_unoptimize_message(&st->offload_msg);
ret = regmap_read(st->regmap, AD4630_REG_ACCESS, &dummy);
out_error:
pm_runtime_mark_last_busy(&st->spi->dev);
pm_runtime_put_autosuspend(&st->spi->dev);
return ret;
}
static const char *const ad4630_average_modes[] = {
"2", "4", "8", "16", "32", "64", "128", "256", "512", "1024",
"2048", "4096", "8192", "16384", "32768", "65536"
};
static const struct iio_enum ad4630_avg_frame_len_enum = {
.items = ad4630_average_modes,
.num_items = ARRAY_SIZE(ad4630_average_modes),
.set = ad4630_set_avg_frame_len,
.get = ad4630_get_avg_frame_len,
};
static const struct iio_chan_spec_ext_info ad4630_ext_info[] = {
IIO_ENUM("sample_averaging", IIO_SHARED_BY_TYPE,
&ad4630_avg_frame_len_enum),
IIO_ENUM_AVAILABLE("sample_averaging", IIO_SHARED_BY_TYPE,
&ad4630_avg_frame_len_enum),
{}
};
#define AD4630_CHAN(_idx, _msk_avail, _storage, _real, _shift, _info) { \
.info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS), \
.info_mask_separate_available = _msk_avail, \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = _idx, \
.scan_index = _idx, \
.ext_info = _info, \
.scan_type = { \
.sign = 's', \
.storagebits = _storage, \
.realbits = _real, \
.shift = _shift, \
}, \
}
/*
* We need the sample size to be 64 bytes when both channels are enabled as the
* HW will always fill in the DMA bus which is 64bits. If we had just 16 bits
* of storage (for example on the AD4630_16_DIFF mode for ad4630-16 ), we would
* have a sample size of 32bits having the 16MSb set to 0 (in theory channel_2
* data) as the HW fills in the channel_1 sample to get the 32bits per channel
* storage.
*/
static const struct ad4630_out_mode ad4030_24_modes[] = {
[AD4630_24_DIFF] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 64, 24, 0, NULL),
},
.data_width = 24,
},
[AD4630_16_DIFF_8_COM] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 64, 16, 8, NULL),
},
.data_width = 24,
},
[AD4630_24_DIFF_8_COM] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 64, 24, 8, NULL),
},
.data_width = 32,
},
[AD4630_30_AVERAGED_DIFF] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 64, 30, 2,
ad4630_ext_info),
},
.data_width = 32,
}
};
static const struct ad4630_out_mode ad4630_16_modes[] = {
[AD4630_16_DIFF] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 32, 16, 0, NULL),
AD4630_CHAN(1, AD4630_CHAN_INFO_NONE, 32, 16, 0, NULL),
},
.data_width = 16,
},
[AD4630_16_DIFF_8_COM] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 32, 16, 8, NULL),
AD4630_CHAN(1, AD4630_CHAN_INFO_NONE, 32, 16, 8, NULL),
},
.data_width = 24,
},
[AD4630_30_AVERAGED_DIFF] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 32, 30, 2,
ad4630_ext_info),
AD4630_CHAN(1, AD4630_CHAN_INFO_NONE, 32, 30, 2,
ad4630_ext_info),
},
.data_width = 32,
}
};
static const struct ad4630_out_mode ad4630_24_modes[] = {
[AD4630_24_DIFF] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 32, 24, 0, NULL),
AD4630_CHAN(1, AD4630_CHAN_INFO_NONE, 32, 24, 0, NULL),
},
.data_width = 24,
},
[AD4630_16_DIFF_8_COM] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 32, 16, 8, NULL),
AD4630_CHAN(1, AD4630_CHAN_INFO_NONE, 32, 16, 8, NULL),
},
.data_width = 24,
},
[AD4630_24_DIFF_8_COM] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 32, 24, 8, NULL),
AD4630_CHAN(1, AD4630_CHAN_INFO_NONE, 32, 24, 8, NULL),
},
.data_width = 32,
},
[AD4630_30_AVERAGED_DIFF] = {
.channels = {
AD4630_CHAN(0, AD4630_CHAN_INFO_NONE, 32, 30, 2,
ad4630_ext_info),
AD4630_CHAN(1, AD4630_CHAN_INFO_NONE, 32, 30, 2,
ad4630_ext_info),
},
.data_width = 32,
}
};
static const struct ad4630_out_mode adaq4224_modes[] = {
[AD4630_24_DIFF] = {
.channels = {
AD4630_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 64, 24, 0, NULL),
},
.data_width = 24,
},
[AD4630_16_DIFF_8_COM] = {
.channels = {
AD4630_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 64, 16, 8, NULL),
},
.data_width = 24,
},
[AD4630_24_DIFF_8_COM] = {
.channels = {
AD4630_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 64, 24, 8, NULL),
},
.data_width = 32,
},
[AD4630_30_AVERAGED_DIFF] = {
.channels = {
AD4630_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 64, 30, 2, ad4630_ext_info),
},
.data_width = 32,
}
};
/* all channels must be enabled */
static const unsigned long ad4630_channel_masks[] = {
GENMASK(1, 0),
0,
};
static const unsigned long ad4030_channel_masks[] = {
BIT(0),
0,
};
/* test pattern is treated as an additional channel */
static const struct ad4630_chip_info ad4630_chip_info[] = {
[ID_AD4030_24] = {
.available_masks = ad4030_channel_masks,
.modes = ad4030_24_modes,
.out_modes_mask = GENMASK(3, 0),
.name = "ad4030-24",
.grade = 0x10,
.min_offset = (int)BIT(23) * -1,
.max_offset = BIT(23) - 1,
.base_word_len = 24,
.n_channels = 1,
},
[ID_AD4032_24] = {
.available_masks = ad4030_channel_masks,
.modes = ad4030_24_modes,
.out_modes_mask = GENMASK(3, 0),
.name = "ad4032-24",
.grade = 0x12,
.min_offset = (int)BIT(23) * -1,
.max_offset = BIT(23) - 1,
.base_word_len = 24,
.n_channels = 1,
},
[ID_AD4630_16] = {
.available_masks = ad4630_channel_masks,
.modes = ad4630_16_modes,
.out_modes_mask = BIT(3) | GENMASK(1, 0),
.name = "ad4630-16",
.grade = 0x03,
.min_offset = (int)BIT(15) * -1,
.max_offset = BIT(15) - 1,
.base_word_len = 16,
.n_channels = 2,
},
[ID_AD4632_16] = {
.available_masks = ad4630_channel_masks,
.modes = ad4630_16_modes,
.out_modes_mask = BIT(3) | GENMASK(1, 0),
.name = "ad4632-16",
.grade = 0x05,
.min_offset = (int)BIT(15) * -1,
.max_offset = BIT(15) - 1,
.base_word_len = 16,
.n_channels = 2,
},
[ID_AD4630_24] = {
.available_masks = ad4630_channel_masks,
.modes = ad4630_24_modes,
.out_modes_mask = GENMASK(3, 0),
.name = "ad4630-24",
.min_offset = (int)BIT(23) * -1,
.max_offset = BIT(23) - 1,
.base_word_len = 24,
.n_channels = 2,
},
[ID_AD4632_24] = {
.available_masks = ad4630_channel_masks,
.modes = ad4630_24_modes,
.out_modes_mask = GENMASK(3, 0),
.name = "ad4632-24",
.grade = 0x2,
.min_offset = (int)BIT(23) * -1,
.max_offset = BIT(23) - 1,
.base_word_len = 24,