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phy: qcom: edp: Postpone clk_set_rate until the PLL is up
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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andersson committed Jun 6, 2022
1 parent f1c018d commit a9b153b
Showing 1 changed file with 16 additions and 12 deletions.
28 changes: 16 additions & 12 deletions drivers/phy/qualcomm/phy-qcom-edp.c
Original file line number Diff line number Diff line change
Expand Up @@ -272,31 +272,30 @@ static int qcom_edp_configure_pll(const struct qcom_edp *edp)
return 0;
}

static int qcom_edp_set_vco_div(const struct qcom_edp *edp)
static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel_freq)
{
const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
unsigned long pixel_freq;
u32 vco_div;

switch (dp_opts->link_rate) {
case 1620:
vco_div = 0x1;
pixel_freq = 1620000000UL / 2;
*pixel_freq = 1620000000UL / 2;
break;

case 2700:
vco_div = 0x1;
pixel_freq = 2700000000UL / 2;
*pixel_freq = 2700000000UL / 2;
break;

case 5400:
vco_div = 0x2;
pixel_freq = 5400000000UL / 4;
*pixel_freq = 5400000000UL / 4;
break;

case 8100:
vco_div = 0x0;
pixel_freq = 8100000000UL / 6;
*pixel_freq = 8100000000UL / 6;
break;

default:
Expand All @@ -306,15 +305,13 @@ static int qcom_edp_set_vco_div(const struct qcom_edp *edp)

writel(vco_div, edp->edp + DP_PHY_VCO_DIV);

clk_set_rate(edp->dp_link_hw.clk, dp_opts->link_rate * 100000);
clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq);

return 0;
}

static int qcom_edp_phy_power_on(struct phy *phy)
{
const struct qcom_edp *edp = phy_get_drvdata(phy);
unsigned long pixel_freq;
int timeout;
int ret;
u32 val;
Expand Down Expand Up @@ -363,7 +360,7 @@ static int qcom_edp_phy_power_on(struct phy *phy)
writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);
writel(0x04, edp->tx1 + TXn_TX_BAND);

ret = qcom_edp_set_vco_div(edp);
ret = qcom_edp_set_vco_div(edp, &pixel_freq);
if (ret)
return ret;

Expand Down Expand Up @@ -409,8 +406,15 @@ static int qcom_edp_phy_power_on(struct phy *phy)

writel(0x19, edp->edp + DP_PHY_CFG);

return readl_poll_timeout(edp->edp + DP_PHY_STATUS,
val, val & BIT(1), 500, 10000);
ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS,
val, val & BIT(1), 500, 10000);
if (ret)
return ret;

clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000);
clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq);

return 0;
}

static int qcom_edp_phy_power_off(struct phy *phy)
Expand Down

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