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bdx_server_ratios.py
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bdx_server_ratios.py
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# -*- coding: latin-1 -*-
#
# auto generated TopDown/TMA 4.8-full-perf description for Intel Xeon E5 v4 (code named Broadwell EP)
# Please see http://ark.intel.com for more details on these CPUs.
#
# References:
# http://bit.ly/tma-ispass14
# http://halobates.de/blog/p/262
# https://sites.google.com/site/analysismethods/yasin-pubs
# https://download.01.org/perfmon/
# https://github.com/andikleen/pmu-tools/wiki/toplev-manual
#
# Helpers
print_error = lambda msg: False
smt_enabled = False
ebs_mode = False
version = "4.8-full-perf"
base_frequency = -1.0
Memory = 0
Average_Frequency = 0.0
num_cores = 1
num_threads = 1
num_sockets = 1
def handle_error(obj, msg):
print_error(msg)
obj.errcount += 1
obj.val = 0
obj.thresh = False
def handle_error_metric(obj, msg):
print_error(msg)
obj.errcount += 1
obj.val = 0
# Constants
Exe_Ports = 8
Mem_L2_Store_Cost = 9
Mem_L3_Weight = 7
Mem_STLB_Hit_Cost = 8
BAClear_Cost = 12
MS_Switches_Cost = 2
Avg_Assist_Cost = 66
Pipeline_Width = 4
OneMillion = 1000000
OneBillion = 1000000000
Energy_Unit = 61
Errata_Whitelist = "BDE69;BDE70"
EBS_Mode = 0
DS = 1
# Aux. formulas
def Backend_Bound_Cycles(self, EV, level):
return (EV("CYCLE_ACTIVITY.STALLS_TOTAL", level) + EV("UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", level) - Few_Uops_Executed_Threshold(self, EV, level) - Frontend_RS_Empty_Cycles(self, EV, level) + EV("RESOURCE_STALLS.SB", level))
def Cycles_0_Ports_Utilized(self, EV, level):
return (EV("UOPS_EXECUTED.CORE:i1:c1", level)) / 2 if smt_enabled else(EV("CYCLE_ACTIVITY.STALLS_TOTAL", level) - Frontend_RS_Empty_Cycles(self, EV, level))
def Cycles_1_Port_Utilized(self, EV, level):
return (EV("UOPS_EXECUTED.CORE:c1", level) - EV("UOPS_EXECUTED.CORE:c2", level)) / 2 if smt_enabled else(EV("UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", level) - EV("UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", level))
def Cycles_2_Ports_Utilized(self, EV, level):
return (EV("UOPS_EXECUTED.CORE:c2", level) - EV("UOPS_EXECUTED.CORE:c3", level)) / 2 if smt_enabled else(EV("UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", level) - EV("UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", level))
def Cycles_3m_Ports_Utilized(self, EV, level):
return (EV("UOPS_EXECUTED.CORE:c3", level) / 2) if smt_enabled else EV("UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", level)
def DurationTimeInSeconds(self, EV, level):
return EV("interval-ms", 0) / 1000
def Execute_Cycles(self, EV, level):
return (EV("UOPS_EXECUTED.CORE:c1", level) / 2) if smt_enabled else EV("UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", level)
def Fetched_Uops(self, EV, level):
return (EV("IDQ.DSB_UOPS", level) + EV("LSD.UOPS", level) + EV("IDQ.MITE_UOPS", level) + EV("IDQ.MS_UOPS", level))
def Few_Uops_Executed_Threshold(self, EV, level):
EV("UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", level)
EV("UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", level)
return EV("UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", level) if (IPC(self, EV, level)> 1.8) else EV("UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", level)
# Floating Point computational (arithmetic) Operations Count
def FLOP_Count(self, EV, level):
return EV("FP_ARITH_INST_RETIRED.SCALAR", level) + 2 * EV("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", level) + 4 * EV("FP_ARITH_INST_RETIRED.4_FLOPS", level) + 8 * EV("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", level)
# Floating Point computational (arithmetic) Operations Count
def FP_Arith_Scalar(self, EV, level):
return EV("FP_ARITH_INST_RETIRED.SCALAR", level)
# Floating Point computational (arithmetic) Operations Count
def FP_Arith_Vector(self, EV, level):
return EV("FP_ARITH_INST_RETIRED.VECTOR", level)
def Frontend_RS_Empty_Cycles(self, EV, level):
EV("RS_EVENTS.EMPTY_CYCLES", level)
return EV("RS_EVENTS.EMPTY_CYCLES", level) if (self.Fetch_Latency.compute(EV)> 0.1) else 0
def HighIPC(self, EV, level):
val = IPC(self, EV, level) / Pipeline_Width
return val
def ITLB_Miss_Cycles(self, EV, level):
return (14 * EV("ITLB_MISSES.STLB_HIT", level) + EV("ITLB_MISSES.WALK_DURATION:c1", level) + 7 * EV("ITLB_MISSES.WALK_COMPLETED", level))
def LOAD_L1_MISS(self, EV, level):
return EV("MEM_LOAD_UOPS_RETIRED.L2_HIT", level) + EV("MEM_LOAD_UOPS_RETIRED.L3_HIT", level) + EV("MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", level) + EV("MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", level) + EV("MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", level)
def LOAD_L1_MISS_NET(self, EV, level):
return LOAD_L1_MISS(self, EV, level) + EV("MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", level) + EV("MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", level) + EV("MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", level) + EV("MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", level)
def LOAD_L3_HIT(self, EV, level):
return EV("MEM_LOAD_UOPS_RETIRED.L3_HIT", level) * (1 + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level) / LOAD_L1_MISS_NET(self, EV, level))
def LOAD_LCL_MEM(self, EV, level):
return EV("MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", level) * (1 + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level) / LOAD_L1_MISS_NET(self, EV, level))
def LOAD_RMT_FWD(self, EV, level):
return EV("MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", level) * (1 + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level) / LOAD_L1_MISS_NET(self, EV, level))
def LOAD_RMT_HITM(self, EV, level):
return EV("MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", level) * (1 + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level) / LOAD_L1_MISS_NET(self, EV, level))
def LOAD_RMT_MEM(self, EV, level):
return EV("MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", level) * (1 + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level) / LOAD_L1_MISS_NET(self, EV, level))
def LOAD_XSNP_HIT(self, EV, level):
return EV("MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", level) * (1 + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level) / LOAD_L1_MISS_NET(self, EV, level))
def LOAD_XSNP_HITM(self, EV, level):
return EV("MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", level) * (1 + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level) / LOAD_L1_MISS_NET(self, EV, level))
def LOAD_XSNP_MISS(self, EV, level):
return EV("MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", level) * (1 + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level) / LOAD_L1_MISS_NET(self, EV, level))
def Mem_L3_Hit_Fraction(self, EV, level):
return EV("MEM_LOAD_UOPS_RETIRED.L3_HIT", level) / (EV("MEM_LOAD_UOPS_RETIRED.L3_HIT", level) + Mem_L3_Weight * EV("MEM_LOAD_UOPS_RETIRED.L3_MISS", level))
def Mem_Lock_St_Fraction(self, EV, level):
return EV("MEM_UOPS_RETIRED.LOCK_LOADS", level) / EV("MEM_UOPS_RETIRED.ALL_STORES", level)
def Memory_Bound_Fraction(self, EV, level):
return (EV("CYCLE_ACTIVITY.STALLS_MEM_ANY", level) + EV("RESOURCE_STALLS.SB", level)) / Backend_Bound_Cycles(self, EV, level)
def Mispred_Clears_Fraction(self, EV, level):
return EV("BR_MISP_RETIRED.ALL_BRANCHES", level) / (EV("BR_MISP_RETIRED.ALL_BRANCHES", level) + EV("MACHINE_CLEARS.COUNT", level))
def ORO_Demand_RFO_C1(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", level)) , level )
def ORO_DRD_Any_Cycles(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", level)) , level )
def ORO_DRD_BW_Cycles(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", level)) , level )
def SQ_Full_Cycles(self, EV, level):
return (EV("OFFCORE_REQUESTS_BUFFER.SQ_FULL", level) / 2) if smt_enabled else EV("OFFCORE_REQUESTS_BUFFER.SQ_FULL", level)
def Store_L2_Hit_Cycles(self, EV, level):
return EV("L2_RQSTS.RFO_HIT", level) * Mem_L2_Store_Cost *(1 - Mem_Lock_St_Fraction(self, EV, level))
def Mem_XSNP_HitM_Cost(self, EV, level):
return 60
def Mem_XSNP_Hit_Cost(self, EV, level):
return 43
def Mem_XSNP_None_Cost(self, EV, level):
return 41
def Mem_Local_DRAM_Cost(self, EV, level):
return 200
def Mem_Remote_DRAM_Cost(self, EV, level):
return 310
def Mem_Remote_HitM_Cost(self, EV, level):
return 200
def Mem_Remote_Fwd_Cost(self, EV, level):
return 180
def Recovery_Cycles(self, EV, level):
return (EV("INT_MISC.RECOVERY_CYCLES_ANY", level) / 2) if smt_enabled else EV("INT_MISC.RECOVERY_CYCLES", level)
def Retire_Fraction(self, EV, level):
return Retired_Slots(self, EV, level) / EV("UOPS_ISSUED.ANY", level)
# Retired slots per Logical Processor
def Retired_Slots(self, EV, level):
return EV("UOPS_RETIRED.RETIRE_SLOTS", level)
# Number of logical processors (enabled or online) on the target system
def Num_CPUs(self, EV, level):
return 8 if smt_enabled else 4
# Instructions Per Cycle (per Logical Processor)
def IPC(self, EV, level):
return EV("INST_RETIRED.ANY", level) / CLKS(self, EV, level)
# Uops Per Instruction
def UopPI(self, EV, level):
val = Retired_Slots(self, EV, level) / EV("INST_RETIRED.ANY", level)
self.thresh = (val > 1.05)
return val
# Uops per taken branch
def UpTB(self, EV, level):
val = Retired_Slots(self, EV, level) / EV("BR_INST_RETIRED.NEAR_TAKEN", level)
self.thresh = val < Pipeline_Width * 1.5
return val
# Cycles Per Instruction (per Logical Processor)
def CPI(self, EV, level):
return 1 / IPC(self, EV, level)
# Per-Logical Processor actual clocks when the Logical Processor is active.
def CLKS(self, EV, level):
return EV("CPU_CLK_UNHALTED.THREAD", level)
# Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)
def SLOTS(self, EV, level):
return Pipeline_Width * CORE_CLKS(self, EV, level)
# The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage.
def Execute_per_Issue(self, EV, level):
return EV("UOPS_EXECUTED.THREAD", level) / EV("UOPS_ISSUED.ANY", level)
# Instructions Per Cycle across hyper-threads (per physical core)
def CoreIPC(self, EV, level):
return EV("INST_RETIRED.ANY", level) / CORE_CLKS(self, EV, level)
# Floating Point Operations Per Cycle
def FLOPc(self, EV, level):
return FLOP_Count(self, EV, level) / CORE_CLKS(self, EV, level)
# Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to Fused-Multiply Add FMA counting - common.
def FP_Arith_Utilization(self, EV, level):
return (FP_Arith_Scalar(self, EV, level) + FP_Arith_Vector(self, EV, level)) / (2 * CORE_CLKS(self, EV, level))
# Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)
def ILP(self, EV, level):
return EV("UOPS_EXECUTED.THREAD", level) / EV("UOPS_EXECUTED.THREAD:c1", level)
# Core actual clocks when any Logical Processor is active on the Physical Core
def CORE_CLKS(self, EV, level):
return ((EV("CPU_CLK_UNHALTED.THREAD", level) / 2) * (1 + EV("CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", level) / EV("CPU_CLK_UNHALTED.REF_XCLK", level))) if ebs_mode else(EV("CPU_CLK_UNHALTED.THREAD_ANY", level) / 2) if smt_enabled else CLKS(self, EV, level)
# Instructions per Load (lower number means higher occurrence rate). Tip: reduce memory accesses. #Link Opt Guide section: Minimize Register Spills
def IpLoad(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("MEM_UOPS_RETIRED.ALL_LOADS", level)
self.thresh = (val < 3)
return val
# Instructions per Store (lower number means higher occurrence rate). Tip: reduce memory accesses. #Link Opt Guide section: Minimize Register Spills
def IpStore(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("MEM_UOPS_RETIRED.ALL_STORES", level)
self.thresh = (val < 8)
return val
# Instructions per Branch (lower number means higher occurrence rate)
def IpBranch(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.ALL_BRANCHES", level)
self.thresh = (val < 8)
return val
# Instructions per (near) call (lower number means higher occurrence rate)
def IpCall(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.NEAR_CALL", level)
self.thresh = (val < 200)
return val
# Instructions per taken branch
def IpTB(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.NEAR_TAKEN", level)
self.thresh = val < Pipeline_Width * 2 + 1
return val
# Branch instructions per taken branch. . Can be used to approximate PGO-likelihood for non-loopy codes.
def BpTkBranch(self, EV, level):
return EV("BR_INST_RETIRED.ALL_BRANCHES", level) / EV("BR_INST_RETIRED.NEAR_TAKEN", level)
# Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate). Reference: Tuning Performance via Metrics with Expectations. https://doi.org/10.1109/LCA.2019.2916408
def IpFLOP(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / FLOP_Count(self, EV, level)
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.
def IpArith(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / (FP_Arith_Scalar(self, EV, level) + FP_Arith_Vector(self, EV, level))
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.
def IpArith_Scalar_SP(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("FP_ARITH_INST_RETIRED.SCALAR_SINGLE", level)
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.
def IpArith_Scalar_DP(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", level)
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.
def IpArith_AVX128(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / (EV("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", level))
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.
def IpArith_AVX256(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / (EV("FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", level))
self.thresh = (val < 10)
return val
# Total number of retired Instructions
def Instructions(self, EV, level):
return EV("INST_RETIRED.ANY", level)
# Average number of Uops retired in cycles where at least one uop has retired.
def Retire(self, EV, level):
return Retired_Slots(self, EV, level) / EV("UOPS_RETIRED.RETIRE_SLOTS:c1", level)
def Execute(self, EV, level):
return EV("UOPS_EXECUTED.THREAD", level) / Execute_Cycles(self, EV, level)
# Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). See section 'Decoded ICache' in Optimization Manual. http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
def DSB_Coverage(self, EV, level):
val = EV("IDQ.DSB_UOPS", level) / Fetched_Uops(self, EV, level)
self.thresh = (val < 0.7) and HighIPC(self, EV, 1)
return val
# Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)
def IpUnknown_Branch(self, EV, level):
return Instructions(self, EV, level) / EV("BACLEARS.ANY", level)
# Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)
def IpMispredict(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_MISP_RETIRED.ALL_BRANCHES", level)
self.thresh = (val < 200)
return val
# Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).
def IpMisp_Indirect(self, EV, level):
val = Instructions(self, EV, level) / (Retire_Fraction(self, EV, level) * EV("BR_MISP_EXEC.INDIRECT", level))
self.thresh = (val < 1000)
return val
# Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)
def Load_Miss_Real_Latency(self, EV, level):
return EV("L1D_PEND_MISS.PENDING", level) / (EV("MEM_LOAD_UOPS_RETIRED.L1_MISS", level) + EV("MEM_LOAD_UOPS_RETIRED.HIT_LFB", level))
# Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)
def MLP(self, EV, level):
return EV("L1D_PEND_MISS.PENDING", level) / EV("L1D_PEND_MISS.PENDING_CYCLES", level)
# L1 cache true misses per kilo instruction for retired demand loads
def L1MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_UOPS_RETIRED.L1_MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache true misses per kilo instruction for retired demand loads
def L2MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_UOPS_RETIRED.L2_MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache misses per kilo instruction for all request types (including speculative)
def L2MPKI_All(self, EV, level):
return 1000 * EV("L2_RQSTS.MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache misses per kilo instruction for all demand loads (including speculative)
def L2MPKI_Load(self, EV, level):
return 1000 * EV("L2_RQSTS.DEMAND_DATA_RD_MISS", level) / EV("INST_RETIRED.ANY", level)
# Offcore requests (L2 cache miss) per kilo instruction for demand RFOs
def L2MPKI_RFO(self, EV, level):
return 1000 * EV("OFFCORE_REQUESTS.DEMAND_RFO", level) / EV("INST_RETIRED.ANY", level)
# L2 cache hits per kilo instruction for all request types (including speculative)
def L2HPKI_All(self, EV, level):
return 1000 *(EV("L2_RQSTS.REFERENCES", level) - EV("L2_RQSTS.MISS", level)) / EV("INST_RETIRED.ANY", level)
# L2 cache hits per kilo instruction for all demand loads (including speculative)
def L2HPKI_Load(self, EV, level):
return 1000 * EV("L2_RQSTS.DEMAND_DATA_RD_HIT", level) / EV("INST_RETIRED.ANY", level)
# L3 cache true misses per kilo instruction for retired demand loads
def L3MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_UOPS_RETIRED.L3_MISS", level) / EV("INST_RETIRED.ANY", level)
def L1D_Cache_Fill_BW(self, EV, level):
return 64 * EV("L1D.REPLACEMENT", level) / OneBillion / Time(self, EV, level)
def L2_Cache_Fill_BW(self, EV, level):
return 64 * EV("L2_LINES_IN.ALL", level) / OneBillion / Time(self, EV, level)
def L3_Cache_Fill_BW(self, EV, level):
return 64 * EV("LONGEST_LAT_CACHE.MISS", level) / OneBillion / Time(self, EV, level)
# Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses
def Page_Walks_Utilization(self, EV, level):
val = (EV("ITLB_MISSES.WALK_DURATION", level) + EV("DTLB_LOAD_MISSES.WALK_DURATION", level) + EV("DTLB_STORE_MISSES.WALK_DURATION", level) + 7 *(EV("DTLB_STORE_MISSES.WALK_COMPLETED", level) + EV("DTLB_LOAD_MISSES.WALK_COMPLETED", level) + EV("ITLB_MISSES.WALK_COMPLETED", level))) / (2 * CORE_CLKS(self, EV, level))
self.thresh = (val > 0.5)
return val
# Average per-core data fill bandwidth to the L1 data cache [GB / sec]
def L1D_Cache_Fill_BW_2T(self, EV, level):
return L1D_Cache_Fill_BW(self, EV, level)
# Average per-core data fill bandwidth to the L2 cache [GB / sec]
def L2_Cache_Fill_BW_2T(self, EV, level):
return L2_Cache_Fill_BW(self, EV, level)
# Average per-core data fill bandwidth to the L3 cache [GB / sec]
def L3_Cache_Fill_BW_2T(self, EV, level):
return L3_Cache_Fill_BW(self, EV, level)
# Average Latency for L2 cache miss demand Loads
def Load_L2_Miss_Latency(self, EV, level):
return EV("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", level) / EV("OFFCORE_REQUESTS.DEMAND_DATA_RD", level)
# Average Parallel L2 cache miss demand Loads
def Load_L2_MLP(self, EV, level):
return EV("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", level) / EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", level)
# Average Parallel L2 cache miss data reads
def Data_L2_MLP(self, EV, level):
return EV("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", level) / EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", level)
# Average CPU Utilization (percentage)
def CPU_Utilization(self, EV, level):
return CPUs_Utilized(self, EV, level) / Num_CPUs(self, EV, level)
# Average number of utilized CPUs
def CPUs_Utilized(self, EV, level):
return EV("CPU_CLK_UNHALTED.REF_TSC", level) / EV("msr/tsc/", 0)
# Measured Average Core Frequency for unhalted processors [GHz]
def Core_Frequency(self, EV, level):
return Turbo_Utilization(self, EV, level) * EV("msr/tsc/", 0) / OneBillion / Time(self, EV, level)
# Measured Average Uncore Frequency for the SoC [GHz]
def Uncore_Frequency(self, EV, level):
return Socket_CLKS(self, EV, level) / 1e9 / Time(self, EV, level)
# Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width
def GFLOPs(self, EV, level):
return (FLOP_Count(self, EV, level) / OneBillion) / Time(self, EV, level)
# Average Frequency Utilization relative nominal frequency
def Turbo_Utilization(self, EV, level):
return CLKS(self, EV, level) / EV("CPU_CLK_UNHALTED.REF_TSC", level)
# Fraction of cycles where both hardware Logical Processors were active
def SMT_2T_Utilization(self, EV, level):
return 1 - EV("CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", level) / (EV("CPU_CLK_UNHALTED.REF_XCLK_ANY", level) / 2) if smt_enabled else 0
# Fraction of cycles spent in the Operating System (OS) Kernel mode
def Kernel_Utilization(self, EV, level):
val = EV("CPU_CLK_UNHALTED.THREAD_P:SUP", level) / EV("CPU_CLK_UNHALTED.THREAD", level)
self.thresh = (val > 0.05)
return val
# Cycles Per Instruction for the Operating System (OS) Kernel mode
def Kernel_CPI(self, EV, level):
return EV("CPU_CLK_UNHALTED.THREAD_P:SUP", level) / EV("INST_RETIRED.ANY_P:SUP", level)
# Average external Memory Bandwidth Use for reads and writes [GB / sec]
def DRAM_BW_Use(self, EV, level):
return (64 *(EV("UNC_M_CAS_COUNT.RD", level) + EV("UNC_M_CAS_COUNT.WR", level)) / OneBillion) / Time(self, EV, level)
# Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches.
def MEM_Read_Latency(self, EV, level):
return OneBillion *(EV("UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182", level) / EV("UNC_C_TOR_INSERTS.MISS_OPCODE:opc=0x182", level)) / (Socket_CLKS(self, EV, level) / Time(self, EV, level))
# Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches
def MEM_Parallel_Reads(self, EV, level):
return EV("UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182", level) / EV("UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182:c1", level)
# Run duration time in seconds
def Time(self, EV, level):
val = EV("interval-s", 0)
self.thresh = (val < 1)
return val
# Socket actual clocks when any core is active on that socket
def Socket_CLKS(self, EV, level):
return EV("UNC_C_CLOCKTICKS:one_unit", level)
# Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]
def IpFarBranch(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.FAR_BRANCH:USER", level)
self.thresh = (val < 1000000)
return val
# Event groups
class Frontend_Bound:
name = "Frontend_Bound"
domain = "Slots"
area = "FE"
level = 1
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['BvFB', 'BvIO', 'TmaL1', 'PGO'])
maxval = None
def compute(self, EV):
try:
self.val = EV("IDQ_UOPS_NOT_DELIVERED.CORE", 1) / SLOTS(self, EV, 1)
self.thresh = (self.val > 0.15)
except ZeroDivisionError:
handle_error(self, "Frontend_Bound zero division")
return self.val
desc = """
This category represents fraction of slots where the
processor's Frontend undersupplies its Backend. Frontend
denotes the first part of the processor core responsible to
fetch operations that are executed later on by the Backend
part. Within the Frontend; a branch predictor predicts the
next address to fetch; cache-lines are fetched from the
memory subsystem; parsed into instructions; and lastly
decoded into micro-operations (uops). Ideally the Frontend
can issue Pipeline_Width uops every cycle to the Backend.
Frontend Bound denotes unutilized issue-slots when there is
no Backend stall; i.e. bubbles where Frontend delivered no
uops while Backend could have accepted them. For example;
stalls due to instruction-cache misses would be categorized
under Frontend Bound."""
class Fetch_Latency:
name = "Fetch_Latency"
domain = "Slots"
area = "FE"
level = 2
htoff = False
sample = ['RS_EVENTS.EMPTY_END']
errcount = 0
sibling = None
metricgroup = frozenset(['Frontend', 'TmaL2'])
maxval = None
def compute(self, EV):
try:
self.val = Pipeline_Width * EV("IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 2) / SLOTS(self, EV, 2)
self.thresh = (self.val > 0.1) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Fetch_Latency zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU was stalled
due to Frontend latency issues. For example; instruction-
cache misses; iTLB misses or fetch stalls after a branch
misprediction are categorized under Frontend Latency. In
such cases; the Frontend eventually delivers no uops for
some period."""
class ICache_Misses:
name = "ICache_Misses"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['BigFootprint', 'BvBC', 'FetchLat', 'IcMiss'])
maxval = None
def compute(self, EV):
try:
self.val = EV("ICACHE.IFDATA_STALL", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "ICache_Misses zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to instruction cache misses.. Using compiler's
Profile-Guided Optimization (PGO) can reduce i-cache misses
through improved hot code layout."""
class ITLB_Misses:
name = "ITLB_Misses"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = ['ITLB_MISSES.WALK_COMPLETED']
errcount = 0
sibling = None
metricgroup = frozenset(['BigFootprint', 'BvBC', 'FetchLat', 'MemoryTLB'])
maxval = None
def compute(self, EV):
try:
self.val = ITLB_Miss_Cycles(self, EV, 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "ITLB_Misses zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Instruction TLB (ITLB) misses.. Consider
large 2M pages for code (selectively prefer hot large-size
function, due to limited 2M entries). Linux options:
standard binaries use libhugetlbfs; Hfsort.. https://github.
com/libhugetlbfs/libhugetlbfs;https://research.fb.com/public
ations/optimizing-function-placement-for-large-scale-data-
center-applications-2/"""
class Branch_Resteers:
name = "Branch_Resteers"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = ['BR_MISP_RETIRED.ALL_BRANCHES']
errcount = 0
sibling = None
metricgroup = frozenset(['FetchLat'])
maxval = None
def compute(self, EV):
try:
self.val = BAClear_Cost *(EV("BR_MISP_RETIRED.ALL_BRANCHES", 3) + EV("MACHINE_CLEARS.COUNT", 3) + EV("BACLEARS.ANY", 3)) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Branch_Resteers zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Branch Resteers. Branch Resteers estimates
the Frontend delay in fetching operations from corrected
path; following all sorts of miss-predicted branches. For
example; branchy code with lots of miss-predictions might
get categorized under Branch Resteers. Note the value of
this node may overlap with its siblings."""
class Mispredicts_Resteers:
name = "Mispredicts_Resteers"
domain = "Clocks"
area = "FE"
level = 4
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['BadSpec', 'BrMispredicts', 'BvMP'])
maxval = None
def compute(self, EV):
try:
self.val = EV("BR_MISP_RETIRED.ALL_BRANCHES", 4) * self.Branch_Resteers.compute(EV) / (EV("BR_MISP_RETIRED.ALL_BRANCHES", 4) + EV("MACHINE_CLEARS.COUNT", 4) + EV("BACLEARS.ANY", 4))
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Mispredicts_Resteers zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Branch Resteers as a result of Branch
Misprediction at execution stage."""
class Clears_Resteers:
name = "Clears_Resteers"
domain = "Clocks"
area = "FE"
level = 4
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['BadSpec', 'MachineClears'])
maxval = None
def compute(self, EV):
try:
self.val = EV("MACHINE_CLEARS.COUNT", 4) * self.Branch_Resteers.compute(EV) / (EV("BR_MISP_RETIRED.ALL_BRANCHES", 4) + EV("MACHINE_CLEARS.COUNT", 4) + EV("BACLEARS.ANY", 4))
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Clears_Resteers zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Branch Resteers as a result of Machine
Clears."""
class Unknown_Branches:
name = "Unknown_Branches"
domain = "Clocks"
area = "FE"
level = 4
htoff = False
sample = ['BACLEARS.ANY']
errcount = 0
sibling = None
metricgroup = frozenset(['BigFootprint', 'BvBC', 'FetchLat'])
maxval = None
def compute(self, EV):
try:
self.val = self.Branch_Resteers.compute(EV) - self.Mispredicts_Resteers.compute(EV) - self.Clears_Resteers.compute(EV)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Unknown_Branches zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to new branch address clears. These are fetched
branches the Branch Prediction Unit was unable to recognize
(e.g. first time the branch is fetched or hitting BTB
capacity limit) hence called Unknown Branches"""
class MS_Switches:
name = "MS_Switches"
domain = "Clocks_Estimated"
area = "FE"
level = 3
htoff = False
sample = ['IDQ.MS_SWITCHES']
errcount = 0
sibling = None
metricgroup = frozenset(['FetchLat', 'MicroSeq'])
maxval = 1.0
def compute(self, EV):
try:
self.val = MS_Switches_Cost * EV("IDQ.MS_SWITCHES", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "MS_Switches zero division")
return self.val
desc = """
This metric estimates the fraction of cycles when the CPU
was stalled due to switches of uop delivery to the Microcode
Sequencer (MS). Commonly used instructions are optimized for
delivery by the DSB (decoded i-cache) or MITE (legacy
instruction decode) pipelines. Certain operations cannot be
handled natively by the execution pipeline; and must be
performed by microcode (small programs injected into the
execution stream). Switching to the MS too often can
negatively impact performance. The MS is designated to
deliver long uop flows required by CISC instructions like
CPUID; or uncommon conditions like Floating Point Assists
when dealing with Denormals."""
class LCP:
name = "LCP"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['FetchLat'])
maxval = None
def compute(self, EV):
try:
self.val = EV("ILD_STALL.LCP", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "LCP zero division")
return self.val
desc = """
This metric represents fraction of cycles CPU was stalled
due to Length Changing Prefixes (LCPs). Using proper
compiler flags or Intel Compiler by default will certainly
avoid this."""
class DSB_Switches:
name = "DSB_Switches"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['DSBmiss', 'FetchLat'])
maxval = None
def compute(self, EV):
try:
self.val = EV("DSB2MITE_SWITCHES.PENALTY_CYCLES", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "DSB_Switches zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to switches from DSB to MITE pipelines. The DSB
(decoded i-cache) is a Uop Cache where the front-end
directly delivers Uops (micro operations) avoiding heavy x86
decoding. The DSB pipeline has shorter latency and delivered
higher bandwidth than the MITE (legacy instruction decode
pipeline). Switching between the two pipelines can cause
penalties hence this metric measures the exposed penalty..
See section 'Optimization for Decoded Icache' in
Optimization Manual:. http://www.intel.com/content/www/us/en
/architecture-and-technology/64-ia-32-architectures-
optimization-manual.html"""
class Fetch_Bandwidth:
name = "Fetch_Bandwidth"
domain = "Slots"
area = "FE"
level = 2
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['FetchBW', 'Frontend', 'TmaL2'])
maxval = None
def compute(self, EV):
try:
self.val = self.Frontend_Bound.compute(EV) - self.Fetch_Latency.compute(EV)
self.thresh = (self.val > 0.2)
except ZeroDivisionError:
handle_error(self, "Fetch_Bandwidth zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU was stalled
due to Frontend bandwidth issues. For example;
inefficiencies at the instruction decoders; or restrictions
for caching in the DSB (decoded uops cache) are categorized
under Fetch Bandwidth. In such cases; the Frontend typically
delivers suboptimal amount of uops to the Backend."""
class MITE:
name = "MITE"
domain = "Slots_Estimated"
area = "FE"
level = 3
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['DSBmiss', 'FetchBW'])
maxval = None
def compute(self, EV):
try:
self.val = (EV("IDQ.ALL_MITE_CYCLES_ANY_UOPS", 3) - EV("IDQ.ALL_MITE_CYCLES_4_UOPS", 3)) / CORE_CLKS(self, EV, 3) / 2
self.thresh = (self.val > 0.1) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "MITE zero division")
return self.val
desc = """
This metric represents Core fraction of cycles in which CPU
was likely limited due to the MITE pipeline (the legacy
decode pipeline). This pipeline is used for code that was
not pre-cached in the DSB or LSD. For example;
inefficiencies due to asymmetric decoders; use of long
immediate or LCP can manifest as MITE fetch bandwidth
bottleneck.. Consider tuning codegen of 'small hotspots'
that can fit in DSB. Read about 'Decoded ICache' in
Optimization Manual:. http://www.intel.com/content/www/us/en
/architecture-and-technology/64-ia-32-architectures-
optimization-manual.html"""
class DSB:
name = "DSB"
domain = "Slots_Estimated"
area = "FE"
level = 3
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['DSB', 'FetchBW'])
maxval = None
def compute(self, EV):
try:
self.val = (EV("IDQ.ALL_DSB_CYCLES_ANY_UOPS", 3) - EV("IDQ.ALL_DSB_CYCLES_4_UOPS", 3)) / CORE_CLKS(self, EV, 3) / 2
self.thresh = (self.val > 0.15) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "DSB zero division")
return self.val
desc = """
This metric represents Core fraction of cycles in which CPU
was likely limited due to DSB (decoded uop cache) fetch
pipeline. For example; inefficient utilization of the DSB
cache structure or bank conflict when reading from it; are
categorized here."""
class Bad_Speculation:
name = "Bad_Speculation"
domain = "Slots"
area = "BAD"
level = 1
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['TmaL1'])
maxval = None
def compute(self, EV):
try:
self.val = (EV("UOPS_ISSUED.ANY", 1) - Retired_Slots(self, EV, 1) + Pipeline_Width * Recovery_Cycles(self, EV, 1)) / SLOTS(self, EV, 1)
self.thresh = (self.val > 0.15)
except ZeroDivisionError:
handle_error(self, "Bad_Speculation zero division")
return self.val
desc = """
This category represents fraction of slots wasted due to
incorrect speculations. This include slots used to issue
uops that do not eventually get retired and slots for which
the issue-pipeline was blocked due to recovery from earlier
incorrect speculation. For example; wasted work due to miss-
predicted branches are categorized under Bad Speculation
category. Incorrect data speculation followed by Memory
Ordering Nukes is another example."""
class Branch_Mispredicts:
name = "Branch_Mispredicts"
domain = "Slots"
area = "BAD"
level = 2
htoff = False
sample = ['BR_MISP_RETIRED.ALL_BRANCHES:pp']
errcount = 0
sibling = None
metricgroup = frozenset(['BadSpec', 'BrMispredicts', 'BvMP', 'TmaL2'])
maxval = None
def compute(self, EV):
try:
self.val = Mispred_Clears_Fraction(self, EV, 2) * self.Bad_Speculation.compute(EV)
self.thresh = (self.val > 0.1) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Branch_Mispredicts zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU has wasted
due to Branch Misprediction. These slots are either wasted
by uops fetched from an incorrectly speculated program path;
or stalls when the out-of-order part of the machine needs to
recover its state from a speculative path.. Using profile
feedback in the compiler may help. Please see the
Optimization Manual for general strategies for addressing
branch misprediction issues..
http://www.intel.com/content/www/us/en/architecture-and-
technology/64-ia-32-architectures-optimization-manual.html"""
class Machine_Clears:
name = "Machine_Clears"
domain = "Slots"
area = "BAD"
level = 2
htoff = False
sample = ['MACHINE_CLEARS.COUNT']
errcount = 0
sibling = None
metricgroup = frozenset(['BadSpec', 'BvMS', 'MachineClears', 'TmaL2'])
maxval = None
def compute(self, EV):
try:
self.val = self.Bad_Speculation.compute(EV) - self.Branch_Mispredicts.compute(EV)
self.thresh = (self.val > 0.1) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Machine_Clears zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU has wasted
due to Machine Clears. These slots are either wasted by
uops fetched prior to the clear; or stalls the out-of-order
portion of the machine needs to recover its state after the
clear. For example; this can happen due to memory ordering
Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code
(SMC) nukes.. See \"Memory Disambiguation\" in Optimization
Manual and:. https://software.intel.com/sites/default/files/
m/d/4/1/d/8/sma.pdf"""
class Backend_Bound:
name = "Backend_Bound"
domain = "Slots"
area = "BE"
level = 1
htoff = False
sample = []
errcount = 0
sibling = None