GitHub - andres-erbsen/curve25519-verilog: Beginnings of a Verilog implementation of Curve25519.

Not tested on real hardware. Do not use unless you really know what you are doing.

69378 cycles per Curve25519 multiplication (as of commit d0a51a88b0) using 15 17-bit multipliers and a bunch of 42-bit adders. Intended to take constant time.

Public Domain.

Name		Name	Last commit message	Last commit date
Latest commit History 35 Commits
doc		doc
.gitignore		.gitignore
Makefile		Makefile
README.md		README.md
curve25519.go		curve25519.go
curve25519.py		curve25519.py
curve25519.v		curve25519.v
curve25519_mock.v		curve25519_mock.v
curve25519_mock_test.v		curve25519_mock_test.v
curve25519_test.v		curve25519_test.v
dh_test.v		dh_test.v
feadd.v		feadd.v
feadd_test.v		feadd_test.v
feexp.v		feexp.v
feexp_test.v		feexp_test.v
femul.v		femul.v
femul_test.v		femul_test.v
fesub.v		fesub.v
fesub_test.v		fesub_test.v

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