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zybo_standalone_audio_0.xpr
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zybo_standalone_audio_0.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="14" Path="/opt/Xilinx/Projects/zybo_standalone_audio_0/zybo_standalone_audio_0.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="1e25023ccff54660832080d12a714c02"/>
<Option Name="Part" Val="xc7z010clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/ip_repo"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/zybo_standalone_audio_0.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/zybo_standalone_audio_0.ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="2"/>
<Option Name="WTModelSimExportSim" Val="2"/>
<Option Name="WTQuestaExportSim" Val="2"/>
<Option Name="WTIesExportSim" Val="2"/>
<Option Name="WTVcsExportSim" Val="2"/>
<Option Name="WTRivieraExportSim" Val="2"/>
<Option Name="WTActivehdlExportSim" Val="2"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/block_design/block_design.bd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../zybo_petalinux_audio_hls/zybo_petalinux_audio_hls.srcs/sources_1/bd/block_design/block_design.bd"/>
<Attr Name="ImportTime" Val="1470589371"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="ip/block_design_axi_i2s_adi_0_0/block_design_axi_i2s_adi_0_0.xci"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="ip/block_design_processing_system7_0_0/block_design_processing_system7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="ip/block_design_axi_interconnect_0_0/block_design_axi_interconnect_0_0.xci"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="ip/block_design_proc_sys_reset_0_0/block_design_proc_sys_reset_0_0.xci"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="hdl/block_design.vhd"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="ip/block_design_auto_pc_0/block_design_auto_pc_0.xci"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="hw_handoff/block_design_bd.tcl"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="hdl/block_design.hwdef"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="hw_handoff/block_design.hwh"/>
<CompFileExtendedInfo CompFileName="block_design.bd" FileRelPathName="block_design_ooc.xdc"/>
</File>
<File Path="$PSRCDIR/sources_1/bd/block_design/hdl/block_design_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="block_design_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/Projects/ZYBO_Master.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../zybo_petalinux_audio_hls/zybo_petalinux_audio_hls.srcs/constrs_1/imports/Projects/ZYBO_Master.xdc"/>
<Attr Name="ImportTime" Val="1470531273"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="block_design_wrapper"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>