You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Describe the solution you'd like
Offer a third layout option, that lays out the pins grouped by their logical function as configured. So GPIO pins would be together (maybe inputs grouped and outputs grouped?), if I2C was used, those pins involved grouped together, UART, SPI etc etc...
Describe alternatives you've considered
The existing layouts
Additional context
For things like uart, it would also give a bit more vertical space and allow for nicer visualizations, alongside the group, instead of the space being scattered across pins.
The text was updated successfully, but these errors were encountered:
Describe the solution you'd like
Offer a third layout option, that lays out the pins grouped by their logical function as configured. So GPIO pins would be together (maybe inputs grouped and outputs grouped?), if I2C was used, those pins involved grouped together, UART, SPI etc etc...
Describe alternatives you've considered
The existing layouts
Additional context
For things like uart, it would also give a bit more vertical space and allow for nicer visualizations, alongside the group, instead of the space being scattered across pins.
The text was updated successfully, but these errors were encountered: