FPGA

It is a verilog code for a FPGA that can be used as a MUX, adder and shift register.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
FPGA.v		FPGA.v
README.md		README.md
a.out		a.out
configure_adder.mem		configure_adder.mem
configure_mux.mem		configure_mux.mem
configure_shifter.mem		configure_shifter.mem
cs203.vcd		cs203.vcd
tb_adder.v		tb_adder.v
tb_mux.v		tb_mux.v
tb_shifter.v		tb_shifter.v

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